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newAMnewAM
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treewide: clean up usages of rustfmt::skip
1 parent e15ae49 commit 8725a3d

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11 files changed

+270
-326
lines changed

11 files changed

+270
-326
lines changed

‎hal/src/aes.rs‎

Lines changed: 161 additions & 180 deletions
Large diffs are not rendered by default.

‎hal/src/dac.rs‎

Lines changed: 4 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -378,13 +378,11 @@ impl Dac {
378378
/// dac.setup_soft_trigger();
379379
/// ```
380380
pub fn setup_soft_trigger(&mut self) {
381-
#[rustfmt::skip]
382381
self.dac.cr.write(|w| {
383-
w
384-
.cen1().normal()
385-
.tsel1().swtrig()
386-
.ten1().enabled()
387-
.en1().enabled()
382+
w.cen1().normal();
383+
w.tsel1().swtrig();
384+
w.ten1().enabled();
385+
w.en1().enabled()
388386
});
389387
}
390388

‎hal/src/dma/mod.rs‎

Lines changed: 12 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -442,19 +442,15 @@ impl AllDma {
442442
/// See [`steal`](Self::steal).
443443
#[inline]
444444
pub unsafe fn pulse_resets(rcc: &mut pac::RCC) {
445-
#[rustfmt::skip]
446445
rcc.ahb1rstr.modify(|_, w| {
447-
w
448-
.dmamux1rst().set_bit()
449-
.dma2rst().set_bit()
450-
.dma1rst().set_bit()
446+
w.dmamux1rst().set_bit();
447+
w.dma2rst().set_bit();
448+
w.dma1rst().set_bit()
451449
});
452-
#[rustfmt::skip]
453450
rcc.ahb1rstr.modify(|_, w| {
454-
w
455-
.dmamux1rst().clear_bit()
456-
.dma2rst().clear_bit()
457-
.dma1rst().clear_bit()
451+
w.dmamux1rst().clear_bit();
452+
w.dma2rst().clear_bit();
453+
w.dma1rst().clear_bit()
458454
});
459455
}
460456

@@ -467,12 +463,10 @@ impl AllDma {
467463
/// See [`steal`](Self::steal).
468464
#[inline]
469465
pub fn enable_clocks(rcc: &mut pac::RCC) {
470-
#[rustfmt::skip]
471466
rcc.ahb1enr.modify(|_, w| {
472-
w
473-
.dmamux1en().enabled()
474-
.dma2en().enabled()
475-
.dma1en().enabled()
467+
w.dmamux1en().enabled();
468+
w.dma2en().enabled();
469+
w.dma1en().enabled()
476470
});
477471
rcc.ahb1enr.read(); // delay after an RCC peripheral clock enabling
478472
}
@@ -505,12 +499,10 @@ impl AllDma {
505499
/// ```
506500
#[inline]
507501
pub unsafe fn disable_clocks(rcc: &mut pac::RCC) {
508-
#[rustfmt::skip]
509502
rcc.ahb1enr.modify(|_, w| {
510-
w
511-
.dmamux1en().disabled()
512-
.dma2en().disabled()
513-
.dma1en().disabled()
503+
w.dmamux1en().disabled();
504+
w.dma2en().disabled();
505+
w.dma1en().disabled()
514506
});
515507
}
516508

‎hal/src/flash.rs‎

Lines changed: 20 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -298,35 +298,32 @@ impl<'a> Flash<'a> {
298298
c1_c2!(self.flash.sr.read().bits(), self.flash.c2sr.read().bits())
299299
}
300300

301-
#[rustfmt::skip]
302301
#[inline(always)]
303302
fn clear_all_err(&mut self) {
304303
c1_c2!(
305304
self.flash.sr.write(|w| {
306-
w
307-
.rderr().clear()
308-
.fasterr().clear()
309-
.misserr().clear()
310-
.pgserr().clear()
311-
.sizerr().clear()
312-
.pgaerr().clear()
313-
.wrperr().clear()
314-
.progerr().clear()
315-
.operr().clear()
316-
.eop().clear()
305+
w.rderr().clear();
306+
w.fasterr().clear();
307+
w.misserr().clear();
308+
w.pgserr().clear();
309+
w.sizerr().clear();
310+
w.pgaerr().clear();
311+
w.wrperr().clear();
312+
w.progerr().clear();
313+
w.operr().clear();
314+
w.eop().clear()
317315
}),
318316
self.flash.c2sr.write(|w| {
319-
w
320-
.rderr().clear()
321-
.fasterr().clear()
322-
.misserr().clear()
323-
.pgserr().clear()
324-
.sizerr().clear()
325-
.pgaerr().clear()
326-
.wrperr().clear()
327-
.progerr().clear()
328-
.operr().clear()
329-
.eop().clear()
317+
w.rderr().clear();
318+
w.fasterr().clear();
319+
w.misserr().clear();
320+
w.pgserr().clear();
321+
w.sizerr().clear();
322+
w.pgaerr().clear();
323+
w.wrperr().clear();
324+
w.progerr().clear();
325+
w.operr().clear();
326+
w.eop().clear()
330327
}),
331328
)
332329
}

‎hal/src/pka.rs‎

Lines changed: 9 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -377,12 +377,10 @@ impl Pka {
377377

378378
#[inline]
379379
fn clear_all_flags(&mut self) {
380-
#[rustfmt::skip]
381380
self.pka.clrfr.write(|w| {
382-
w
383-
.addrerrfc().set_bit()
384-
.ramerrfc().set_bit()
385-
.procendfc().set_bit()
381+
w.addrerrfc().set_bit();
382+
w.ramerrfc().set_bit();
383+
w.procendfc().set_bit()
386384
});
387385
}
388386

@@ -412,15 +410,13 @@ impl Pka {
412410

413411
#[inline]
414412
fn start_process(&mut self, mode: MODE_A) {
415-
#[rustfmt::skip]
416413
self.pka.cr.write(|w| {
417-
w
418-
.addrerrie().enabled()
419-
.ramerrie().enabled()
420-
.procendie().enabled()
421-
.mode().variant(mode)
422-
.start().set_bit()
423-
.en().set_bit()
414+
w.addrerrie().enabled();
415+
w.ramerrie().enabled();
416+
w.procendie().enabled();
417+
w.mode().variant(mode);
418+
w.start().set_bit();
419+
w.en().set_bit()
424420
});
425421
}
426422

‎hal/src/pwr.rs‎

Lines changed: 6 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -65,19 +65,15 @@ impl WakeupPin {
6565
/// ```
6666
#[inline]
6767
pub fn setup_wakeup_pins(pwr: &mut pac::PWR, wp1: WakeupPin, wp2: WakeupPin, wp3: WakeupPin) {
68-
#[rustfmt::skip]
6968
pwr.cr3.modify(|_, w| {
70-
w
71-
.ewup1().bit(wp1.en())
72-
.ewup2().bit(wp2.en())
73-
.ewup3().bit(wp3.en())
69+
w.ewup1().bit(wp1.en());
70+
w.ewup2().bit(wp2.en());
71+
w.ewup3().bit(wp3.en())
7472
});
75-
#[rustfmt::skip]
7673
pwr.cr4.modify(|_, w| {
77-
w
78-
.wp1().bit(wp1.edge())
79-
.wp2().bit(wp2.edge())
80-
.wp3().bit(wp3.edge())
74+
w.wp1().bit(wp1.edge());
75+
w.wp2().bit(wp2.edge());
76+
w.wp3().bit(wp3.edge())
8177
});
8278
}
8379

‎hal/src/rng.rs‎

Lines changed: 18 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -87,32 +87,28 @@ impl Rng {
8787

8888
// RNG configuration A
8989
// see table 131 "RNG configurations" in the reference manual
90-
#[rustfmt::skip]
9190
rng.cr.write(|w| {
92-
w
93-
.condrst().set_bit()
94-
.nistc().set_bit()
95-
.rng_config1().config_a()
96-
.clkdiv().bits(0x0)
97-
.rng_config2().config_a_b()
98-
.rng_config3().config_a()
99-
.ced().enabled()
100-
.ie().disabled() // interrupt enable
101-
.rngen().set_bit()
91+
w.condrst().set_bit();
92+
w.nistc().set_bit();
93+
w.rng_config1().config_a();
94+
w.clkdiv().bits(0x0);
95+
w.rng_config2().config_a_b();
96+
w.rng_config3().config_a();
97+
w.ced().enabled();
98+
w.ie().disabled(); // interrupt enable
99+
w.rngen().set_bit()
102100
});
103101

104-
#[rustfmt::skip]
105102
rng.cr.write(|w| {
106-
w
107-
.condrst().clear_bit()
108-
.nistc().set_bit()
109-
.rng_config1().config_a()
110-
.clkdiv().bits(0x0)
111-
.rng_config2().config_a_b()
112-
.rng_config3().config_a()
113-
.ced().clear_bit()
114-
.ie().disabled() // interrupt enable
115-
.rngen().set_bit()
103+
w.condrst().clear_bit();
104+
w.nistc().set_bit();
105+
w.rng_config1().config_a();
106+
w.clkdiv().bits(0x0);
107+
w.rng_config2().config_a_b();
108+
w.rng_config3().config_a();
109+
w.ced().clear_bit();
110+
w.ie().disabled(); // interrupt enable
111+
w.rngen().set_bit()
116112
});
117113

118114
// when CONDRST is set to 0 by software its value goes to 0 when the

‎hal/src/rtc.rs‎

Lines changed: 14 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -300,16 +300,14 @@ impl Rtc {
300300
let st: u8 = second / 10;
301301
let su: u8 = second % 10;
302302

303-
#[rustfmt::skip]
304303
self.rtc.tr.write(|w| {
305-
w
306-
.pm().clear_bit() // 24h format
307-
.ht().bits(ht)
308-
.hu().bits(hu)
309-
.mnt().bits(mnt)
310-
.mnu().bits(mnu)
311-
.st().bits(st)
312-
.su().bits(su)
304+
w.pm().clear_bit(); // 24h format
305+
w.ht().bits(ht);
306+
w.hu().bits(hu);
307+
w.mnt().bits(mnt);
308+
w.mnu().bits(mnu);
309+
w.st().bits(st);
310+
w.su().bits(su)
313311
});
314312

315313
let year: i32 = date_time.year();
@@ -327,16 +325,14 @@ impl Rtc {
327325
let dt: u8 = day / 10;
328326
let du: u8 = day % 10;
329327

330-
#[rustfmt::skip]
331328
self.rtc.dr.write(|w| unsafe {
332-
w
333-
.yt().bits(yt)
334-
.yu().bits(yu)
335-
.wdu().bits(wdu)
336-
.mt().bit(mt)
337-
.mu().bits(mu)
338-
.dt().bits(dt)
339-
.du().bits(du)
329+
w.yt().bits(yt);
330+
w.yu().bits(yu);
331+
w.wdu().bits(wdu);
332+
w.mt().bit(mt);
333+
w.mu().bits(mu);
334+
w.dt().bits(dt);
335+
w.du().bits(du)
340336
});
341337

342338
// exit initialization mode

‎hal/src/spi.rs‎

Lines changed: 16 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -1122,17 +1122,15 @@ impl Spi3<SgMiso, SgMosi> {
11221122
Self::enable_clock(rcc);
11231123
unsafe { Self::pulse_reset(rcc) };
11241124

1125-
#[rustfmt::skip]
11261125
spi.cr1.write(|w| {
1127-
w
1128-
.ssi().set_bit()
1129-
.ssm().set_bit()
1130-
.spe().set_bit()
1131-
.br().bits(div as u8)
1132-
.mstr().set_bit()
1133-
// hard coded because we know the SPI mode of the radio
1134-
.cpol().idle_low()
1135-
.cpha().first_edge()
1126+
w.ssi().set_bit();
1127+
w.ssm().set_bit();
1128+
w.spe().set_bit();
1129+
w.br().bits(div as u8);
1130+
w.mstr().set_bit();
1131+
// hard coded because we know the SPI mode of the radio
1132+
w.cpol().idle_low();
1133+
w.cpha().first_edge()
11361134
});
11371135
spi.cr2.write(|w| w.frxth().quarter());
11381136

@@ -1169,17 +1167,15 @@ impl<MISODMA: DmaCh, MOSIDMA: DmaCh> Spi3<MISODMA, MOSIDMA> {
11691167
Self::enable_clock(rcc);
11701168
unsafe { Self::pulse_reset(rcc) };
11711169

1172-
#[rustfmt::skip]
11731170
spi.cr1.write(|w| {
1174-
w
1175-
.ssi().set_bit()
1176-
.ssm().set_bit()
1177-
.spe().set_bit()
1178-
.br().bits(div as u8)
1179-
.mstr().set_bit()
1180-
// hard coded because we know the SPI mode of the radio
1181-
.cpol().idle_low()
1182-
.cpha().first_edge()
1171+
w.ssi().set_bit();
1172+
w.ssm().set_bit();
1173+
w.spe().set_bit();
1174+
w.br().bits(div as u8);
1175+
w.mstr().set_bit();
1176+
// hard coded because we know the SPI mode of the radio
1177+
w.cpol().idle_low();
1178+
w.cpha().first_edge()
11831179
});
11841180

11851181
mosi_dma.set_cr(dma::Cr::DISABLE);

‎testsuite/src/i2c.rs‎

Lines changed: 4 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -54,13 +54,11 @@ mod tests {
5454
.oa1()
5555
.bits((LOOPBACK_ADDR << 1) as u16)
5656
});
57-
#[rustfmt::skip]
5857
i2c2.cr1.modify(|_, w| {
59-
w
60-
.gcen().set_bit() // general call enable
61-
.errie().enabled() // enable error IRQs
62-
.addrie().enabled() // secondary address match IRQ
63-
.pe().enabled() // re-enable peripheral
58+
w.gcen().set_bit(); // general call enable
59+
w.errie().enabled(); // enable error IRQs
60+
w.addrie().enabled(); // secondary address match IRQ
61+
w.pe().enabled() // re-enable peripheral
6462
});
6563

6664
unsafe {

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