rcc: add LSCO functionality

Author: newAM

CHANGELOG.md

@@ -4,6 +4,10 @@ All notable changes to this project will be documented in this file.
 The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/),
 and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
 
+## [Unreleased]
+### Added
+- Added `rcc::Lsco` to use the low-speed oscillator output.
+
 ## [0.5.1] - 2022-05-14
 ### Added
 - Added `Rtc::alarm_{a,b}` to get the alarm value.

hal/src/gpio.rs

@@ -265,6 +265,7 @@ pub(crate) mod sealed {
     af_trait!(Tim17Ch1, set_tim17_ch1_af);
     af_trait!(Tim17Bkin, set_tim17_bkin_af);
     af_trait!(Tim17Ch1n, set_tim17_ch1n_af);
+    af_trait!(Lsco, set_lsco_af);
 
     /// Indicate a GPIO pin can be sampled by the ADC.
     pub trait AdcCh {
@@ -592,6 +593,8 @@ pub mod pins {
         };
     }
 
+    impl_af!(Lsco, A2, set_lsco_af, 0);
+
     impl_af!(LpTim1Out, A4, set_lptim1_out_af, 1);
     impl_af!(LpTim1Out, A14, set_lptim1_out_af, 1);
     impl_af!(LpTim1Out, B2, set_lptim1_out_af, 1);

hal/src/rcc.rs

@@ -10,6 +10,7 @@ use crate::{pac, Ratio};
 use cortex_m::{interrupt::CriticalSection, peripheral::syst::SystClkSource};
 
 use pac::flash::acr::LATENCY_A;
+pub use pac::rcc::bdcr::LSCOSEL_A as LscoSel;
 pub use pac::rcc::csr::LSIPRE_A as LsiPre;
 
 fn hclk3_prescaler_div(rcc: &pac::RCC) -> u16 {
@@ -959,3 +960,101 @@ pub unsafe fn pulse_reset_backup_domain(rcc: &mut pac::RCC, pwr: &mut pac::PWR)
     rcc.bdcr.modify(|_, w| w.bdrst().set_bit());
     rcc.bdcr.modify(|_, w| w.bdrst().clear_bit());
 }
+
+/// Low-speed oscillator output pin.
+#[derive(Debug)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub struct Lsco {
+    pin: crate::gpio::pins::A2,
+}
+
+impl Lsco {
+    /// Enable the low-speed oscillator output.
+    ///
+    /// # Safety
+    ///
+    /// 1. Backup domain write protect must be disabled.
+    /// 2. The selected clock must be enabled for system use.
+    ///
+    /// # Example
+    ///
+    /// ```no_run
+    /// use stm32wlxx_hal::{
+    ///     gpio::PortA,
+    ///     pac,
+    ///     rcc::{Lsco, LscoSel},
+    /// };
+    ///
+    /// let mut dp: pac::Peripherals = pac::Peripherals::take().unwrap();
+    ///
+    /// // disable backup domain write protect
+    /// dp.PWR.cr1.modify(|_, w| w.dbp().enabled());
+    ///
+    /// // enable the LSE clock
+    /// dp.RCC
+    ///     .bdcr
+    ///     .modify(|_, w| w.lseon().on().lsesysen().enabled());
+    /// while dp.RCC.bdcr.read().lserdy().is_not_ready() {}
+    /// while dp.RCC.bdcr.read().lsesysrdy().is_not_ready() {}
+    ///
+    /// let gpioa: PortA = PortA::split(dp.GPIOA, &mut dp.RCC);
+    /// let a2: Lsco = cortex_m::interrupt::free(|cs| unsafe {
+    ///     Lsco::enable(gpioa.a2, LscoSel::LSE, &mut dp.RCC, cs)
+    /// });
+    /// ```
+    #[inline]
+    pub unsafe fn enable(
+        mut a2: crate::gpio::pins::A2,
+        sel: LscoSel,
+        rcc: &mut pac::RCC,
+        cs: &CriticalSection,
+    ) -> Self {
+        use crate::gpio::sealed::Lsco;
+        a2.set_lsco_af(cs);
+        rcc.bdcr
+            .modify(|_, w| w.lscoen().enabled().lscosel().variant(sel));
+        Self { pin: a2 }
+    }
+
+    /// Disable the low-speed oscillator output.
+    ///
+    /// # Safety
+    ///
+    /// 1. Backup domain write protect must be disabled.
+    ///
+    /// # Example
+    ///
+    /// ```no_run
+    /// use stm32wlxx_hal::{
+    ///     gpio::{pins, PortA},
+    ///     pac,
+    ///     rcc::{Lsco, LscoSel},
+    /// };
+    ///
+    /// let mut dp: pac::Peripherals = pac::Peripherals::take().unwrap();
+    ///
+    /// // disable backup domain write protect
+    /// dp.PWR.cr1.modify(|_, w| w.dbp().enabled());
+    ///
+    /// // enable the LSE clock
+    /// dp.RCC
+    ///     .bdcr
+    ///     .modify(|_, w| w.lseon().on().lsesysen().enabled());
+    /// while dp.RCC.bdcr.read().lserdy().is_not_ready() {}
+    /// while dp.RCC.bdcr.read().lsesysrdy().is_not_ready() {}
+    ///
+    /// let gpioa: PortA = PortA::split(dp.GPIOA, &mut dp.RCC);
+    /// let lsco: Lsco = cortex_m::interrupt::free(|cs| unsafe {
+    ///     Lsco::enable(gpioa.a2, LscoSel::LSE, &mut dp.RCC, cs)
+    /// });
+    ///
+    /// // ... use LSCO
+    ///
+    /// let a2: pins::A2 = unsafe { lsco.disable(&mut dp.RCC) };
+    /// ```
+    #[inline]
+    pub unsafe fn disable(self, rcc: &mut pac::RCC) -> crate::gpio::pins::A2 {
+        rcc.bdcr.modify(|_, w| w.lscoen().disabled());
+        self.pin
+    }
+}