Skip to content

Commit cd43b01

Browse files
newAMnewAM
authored
util: remove reset_cycle_count
1 parent 8cdc478 commit cd43b01

File tree

13 files changed

+95
-123
lines changed

13 files changed

+95
-123
lines changed

‎CHANGELOG.md‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -17,6 +17,9 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
1717
- `subghz::Stats`
1818
- `subghz::Status`
1919

20+
### Removed
21+
- Removed `util::reset_cycle_count`; this functionality is now in `cortex-m`.
22+
2023
## [0.3.0] - 2021-12-20
2124
### Added
2225
- Added `info::Core::CT` to get the CPU core at compile time.

‎Cargo.lock‎

Lines changed: 12 additions & 12 deletions
Some generated files are not rendered by default. Learn more about customizing how changed files appear on GitHub.

‎hal/src/util.rs‎

Lines changed: 0 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -22,27 +22,3 @@ pub fn new_delay(syst: pac::SYST, rcc: &pac::RCC) -> Delay {
2222
crate::rcc::cpu_systick_hz(rcc, SystClkSource::Core),
2323
)
2424
}
25-
26-
/// Reset the cycle counter to zero.
27-
///
28-
/// This function will be removed upon the next release of [`cortex_m`] that
29-
/// includes this functionality. See [#347] for details.
30-
///
31-
/// # Example
32-
///
33-
/// ```no_run
34-
/// use stm32wlxx_hal::{pac, util::reset_cycle_count};
35-
///
36-
/// let mut cp = pac::CorePeripherals::take().unwrap();
37-
/// cp.DCB.enable_trace();
38-
/// cp.DWT.enable_cycle_counter();
39-
/// reset_cycle_count(&mut cp.DWT);
40-
/// ```
41-
///
42-
/// [#347]: https://github.com/rust-embedded/cortex-m/pull/347
43-
#[allow(unused_variables)]
44-
#[inline]
45-
pub fn reset_cycle_count(dwt: &mut pac::DWT) {
46-
const DWT_CYCCNT: *mut u32 = 0xE0001004 as *mut u32;
47-
unsafe { DWT_CYCCNT.write_volatile(0) };
48-
}

‎testsuite/src/adc.rs‎

Lines changed: 17 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,7 @@ use nucleo_wl55jc_bsp::hal::{
99
cortex_m::{self, delay::Delay},
1010
pac::{self, DWT},
1111
rcc,
12-
util::{new_delay, reset_cycle_count},
12+
util::new_delay,
1313
};
1414
use panic_probe as _;
1515

@@ -19,7 +19,7 @@ const FREQ_RATIO: u32 = FREQ / ADC_FREQ;
1919
const CYC_PER_US: u32 = FREQ / 1000 / 1000;
2020

2121
// WARNING will wrap-around eventually, use this for relative timing only
22-
defmt::timestamp!("{=u32:us}", DWT::get_cycle_count() / CYC_PER_US);
22+
defmt::timestamp!("{=u32:us}", DWT::cycle_count() / CYC_PER_US);
2323

2424
fn validate_vbat(sample: u16) {
2525
const EXPECTED: i16 = 4096 / 3;
@@ -56,7 +56,7 @@ mod tests {
5656

5757
cp.DCB.enable_trace();
5858
cp.DWT.enable_cycle_counter();
59-
reset_cycle_count(&mut cp.DWT);
59+
cp.DWT.set_cycle_count(0);
6060

6161
TestArgs {
6262
adc,
@@ -71,9 +71,9 @@ mod tests {
7171
defmt::assert!(!ta.adc.is_enabled());
7272

7373
// disable -> enable
74-
let start: u32 = DWT::get_cycle_count();
74+
let start: u32 = DWT::cycle_count();
7575
ta.adc.enable();
76-
let end: u32 = DWT::get_cycle_count();
76+
let end: u32 = DWT::cycle_count();
7777
compiler_fence(SeqCst);
7878
let elapsed: u32 = end - start;
7979
defmt::info!(
@@ -90,9 +90,9 @@ mod tests {
9090
defmt::assert!(ta.adc.is_enabled());
9191

9292
// enable -> disable
93-
let start: u32 = DWT::get_cycle_count();
93+
let start: u32 = DWT::cycle_count();
9494
ta.adc.disable();
95-
let end: u32 = DWT::get_cycle_count();
95+
let end: u32 = DWT::cycle_count();
9696
compiler_fence(SeqCst);
9797
let elapsed: u32 = end - start;
9898
defmt::info!(
@@ -260,9 +260,9 @@ mod tests {
260260
ta.adc.enable_vreg();
261261
ta.delay.delay_us(u32::from(adc::T_ADCVREG_SETUP_MICROS));
262262
ta.adc.start_calibrate();
263-
let start: u32 = DWT::get_cycle_count();
263+
let start: u32 = DWT::cycle_count();
264264
while Adc::isr().eocal().is_not_complete() {}
265-
let end: u32 = DWT::get_cycle_count();
265+
let end: u32 = DWT::cycle_count();
266266
compiler_fence(SeqCst);
267267
let elapsed: u32 = end - start;
268268
defmt::info!(
@@ -272,9 +272,9 @@ mod tests {
272272
);
273273

274274
let _: bool = ta.adc.start_enable();
275-
let start: u32 = DWT::get_cycle_count();
275+
let start: u32 = DWT::cycle_count();
276276
while Adc::isr().adrdy().is_not_ready() {}
277-
let end: u32 = DWT::get_cycle_count();
277+
let end: u32 = DWT::cycle_count();
278278
let elapsed: u32 = end - start;
279279
defmt::info!(
280280
"Enable cycles: CPU {} ADC {}",
@@ -283,9 +283,9 @@ mod tests {
283283
);
284284

285285
ta.adc.start_chsel(adc::Ch::Vbat.mask());
286-
let start: u32 = DWT::get_cycle_count();
286+
let start: u32 = DWT::cycle_count();
287287
while Adc::isr().ccrdy().is_not_complete() {}
288-
let end: u32 = DWT::get_cycle_count();
288+
let end: u32 = DWT::cycle_count();
289289
compiler_fence(SeqCst);
290290
let elapsed: u32 = end - start;
291291
defmt::info!(
@@ -296,9 +296,9 @@ mod tests {
296296

297297
ta.adc.set_max_sample_time();
298298
ta.adc.start_conversion();
299-
let start: u32 = DWT::get_cycle_count();
299+
let start: u32 = DWT::cycle_count();
300300
while Adc::isr().eoc().is_not_complete() {}
301-
let end: u32 = DWT::get_cycle_count();
301+
let end: u32 = DWT::cycle_count();
302302
compiler_fence(SeqCst);
303303
let elapsed: u32 = end - start;
304304
defmt::info!(
@@ -324,9 +324,9 @@ mod tests {
324324
ta.adc.stop_conversion();
325325

326326
// wait 161 ADC cycles (maximum sample time) before checking
327-
let start: u32 = DWT::get_cycle_count();
327+
let start: u32 = DWT::cycle_count();
328328
loop {
329-
let elapsed: u32 = (DWT::get_cycle_count() - start) * FREQ_RATIO;
329+
let elapsed: u32 = (DWT::cycle_count() - start) * FREQ_RATIO;
330330
if elapsed > u32::from(adc::Ts::MAX.cycles().to_integer()) + 1 {
331331
break;
332332
}

‎testsuite/src/aes.rs‎

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,6 @@ use nucleo_wl55jc_bsp::hal::{
1414
aes::{Aes, AesWrapClk, SwapMode},
1515
cortex_m::{self, peripheral::DWT},
1616
pac, rcc,
17-
util::reset_cycle_count,
1817
};
1918
use panic_probe as _;
2019

@@ -1478,7 +1477,7 @@ const FREQ: u32 = 48_000_000;
14781477
const CYC_PER_US: u32 = FREQ / 1000 / 1000;
14791478

14801479
// WARNING will wrap-around eventually, use this for relative timing only
1481-
defmt::timestamp!("{=u32:us}", DWT::get_cycle_count() / CYC_PER_US);
1480+
defmt::timestamp!("{=u32:us}", DWT::cycle_count() / CYC_PER_US);
14821481

14831482
const ZERO_16B: [u32; 4] = [0; 4];
14841483
const ZERO_32B: [u32; 8] = [0; 8];
@@ -1488,9 +1487,9 @@ fn stopwatch<F>(f: F) -> u32
14881487
where
14891488
F: FnOnce() -> (),
14901489
{
1491-
let start: u32 = DWT::get_cycle_count();
1490+
let start: u32 = DWT::cycle_count();
14921491
f();
1493-
let end: u32 = DWT::get_cycle_count();
1492+
let end: u32 = DWT::cycle_count();
14941493
end.wrapping_sub(start)
14951494
}
14961495

@@ -1563,7 +1562,7 @@ mod tests {
15631562

15641563
cp.DCB.enable_trace();
15651564
cp.DWT.enable_cycle_counter();
1566-
reset_cycle_count(&mut cp.DWT);
1565+
cp.DWT.set_cycle_count(0);
15671566

15681567
Aes::new(dp.AES, &mut dp.RCC)
15691568
}

‎testsuite/src/flash.rs‎

Lines changed: 10 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,6 @@ use nucleo_wl55jc_bsp::hal::{
1010
pac::{self, DWT},
1111
rcc,
1212
rng::{self, Rng},
13-
util::reset_cycle_count,
1413
};
1514
use panic_probe as _;
1615
use rand::Rng as RngTrait;
@@ -20,7 +19,7 @@ const FREQ: u32 = 48_000_000;
2019
const CYC_PER_MICRO: u32 = FREQ / 1000 / 1000;
2120

2221
// WARNING will wrap-around eventually, use this for relative timing only
23-
defmt::timestamp!("{=u32:us}", DWT::get_cycle_count() / CYC_PER_MICRO);
22+
defmt::timestamp!("{=u32:us}", DWT::cycle_count() / CYC_PER_MICRO);
2423

2524
#[cortex_m_rt::exception]
2625
#[allow(non_snake_case)]
@@ -57,7 +56,7 @@ mod tests {
5756

5857
cp.DCB.enable_trace();
5958
cp.DWT.enable_cycle_counter();
60-
reset_cycle_count(&mut cp.DWT);
59+
cp.DWT.set_cycle_count(0);
6160

6261
let mut rng: Rng = Rng::new(dp.RNG, rng::Clk::MSI, &mut dp.RCC);
6362

@@ -101,9 +100,9 @@ mod tests {
101100

102101
let mut flash: Flash = Flash::unlock(&mut ta.flash);
103102

104-
let start: u32 = DWT::get_cycle_count();
103+
let start: u32 = DWT::cycle_count();
105104
unwrap!(unsafe { flash.page_erase(ta.page.clone()) });
106-
let end: u32 = DWT::get_cycle_count();
105+
let end: u32 = DWT::cycle_count();
107106
let elapsed: u32 = end.wrapping_sub(start);
108107

109108
defmt::info!(
@@ -127,9 +126,9 @@ mod tests {
127126

128127
let mut flash: Flash = Flash::unlock(&mut ta.flash);
129128

130-
let start: u32 = DWT::get_cycle_count();
129+
let start: u32 = DWT::cycle_count();
131130
unwrap!(unsafe { flash.fast_program(BUF.as_ptr(), ta.addr as *mut u64) });
132-
let end: u32 = DWT::get_cycle_count();
131+
let end: u32 = DWT::cycle_count();
133132
let elapsed: u32 = end.wrapping_sub(start);
134133

135134
defmt::info!(
@@ -162,9 +161,9 @@ mod tests {
162161

163162
let mut flash: Flash = Flash::unlock(&mut ta.flash);
164163

165-
let start: u32 = DWT::get_cycle_count();
164+
let start: u32 = DWT::cycle_count();
166165
unwrap!(unsafe { flash.standard_program(&data, ta.addr as *mut u64) });
167-
let end: u32 = DWT::get_cycle_count();
166+
let end: u32 = DWT::cycle_count();
168167
let elapsed: u32 = end.wrapping_sub(start);
169168

170169
defmt::info!(
@@ -235,9 +234,9 @@ mod tests {
235234

236235
let mut flash: Flash = Flash::unlock(&mut ta.flash);
237236

238-
let start: u32 = DWT::get_cycle_count();
237+
let start: u32 = DWT::cycle_count();
239238
unwrap!(unsafe { flash.standard_program_generic(&data, ta.addr as *mut TestStruct) });
240-
let end: u32 = DWT::get_cycle_count();
239+
let end: u32 = DWT::cycle_count();
241240
let elapsed: u32 = end.wrapping_sub(start);
242241

243242
let size = core::mem::size_of::<TestStruct>();

‎testsuite/src/info.rs‎

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -8,15 +8,14 @@ use nucleo_wl55jc_bsp::hal::{
88
info::{self, Core, Uid64},
99
pac::{self, DWT},
1010
rcc,
11-
util::reset_cycle_count,
1211
};
1312
use panic_probe as _;
1413

1514
const FREQ: u32 = 48_000_000;
1615
const CYC_PER_MICRO: u32 = FREQ / 1000 / 1000;
1716

1817
// WARNING will wrap-around eventually, use this for relative timing only
19-
defmt::timestamp!("{=u32:us}", DWT::get_cycle_count() / CYC_PER_MICRO);
18+
defmt::timestamp!("{=u32:us}", DWT::cycle_count() / CYC_PER_MICRO);
2019

2120
#[defmt_test::tests]
2221
mod tests {
@@ -33,7 +32,7 @@ mod tests {
3332

3433
cp.DCB.enable_trace();
3534
cp.DWT.enable_cycle_counter();
36-
reset_cycle_count(&mut cp.DWT);
35+
cp.DWT.set_cycle_count(0);
3736
}
3837

3938
#[test]

0 commit comments

Comments
 (0)