diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml
index 80b7462b8e9..c775f135ba5 100644
--- a/.github/workflows/ci.yml
+++ b/.github/workflows/ci.yml
@@ -24,7 +24,7 @@ jobs:
           - "stm32wl5x_cm4"
           - "stm32wle5"
         toolchain:
-          - "1.62" # MSRV
+          - "1.85" # MSRV
           - "beta"
         exclude:
           - mcu: "stm32wl5x_cm0p"
diff --git a/CHANGELOG.md b/CHANGELOG.md
index 50d073a8c75..14695c0ac0b 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -9,7 +9,8 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - Renamed function TcxoMode::set_txco_trim() to TcxoMode::set_tcxo_trim() to correct spelling.
 - Renamed enum CmdStatus::Avaliable to CmdStatus::Available to correct spelling.
 - Updated minimum `chrono` version to `0.4.23` to satisfy `cargo-audit`.
-- Changed minimum supported rust version from 1.60 to 1.62.
+- Changed the edition from 2021 to 2024.
+- Changed minimum supported rust version from 1.60 to 1.85.
 
 ### Fixed
 - Added a missing `must_use` in `SleepCfg::set_startup`.
diff --git a/Cargo.lock b/Cargo.lock
index 374e49fddd2..917f02a1eaa 100644
--- a/Cargo.lock
+++ b/Cargo.lock
@@ -1,6 +1,6 @@
 # This file is automatically @generated by Cargo.
 # It is not intended for manual editing.
-version = 3
+version = 4
 
 [[package]]
 name = "aead"
@@ -349,7 +349,7 @@ dependencies = [
 
 [[package]]
 name = "examples"
-version = "0.1.0"
+version = "0.6.1"
 dependencies = [
  "cortex-m",
  "cortex-m-rt",
@@ -798,7 +798,7 @@ dependencies = [
 
 [[package]]
 name = "testsuite"
-version = "0.1.0"
+version = "0.6.1"
 dependencies = [
  "aes-gcm",
  "cortex-m",
diff --git a/Cargo.toml b/Cargo.toml
index 8c3aae67a84..fb1ea07b0e3 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -43,3 +43,18 @@ incremental = false
 lto = false
 opt-level = 3 
 overflow-checks = false
+
+[workspace.package]
+edition = "2024"
+authors = ["Alex Martens <alex@thinglab.org>"]
+repository = "https://github.com/stm32-rs/stm32wlxx-hal"
+license = "MIT OR Apache-2.0"
+# To update version change:
+# * BSP versions
+# * BSP HAL dependency versions
+# * README
+# * BSP READMES
+# * lock file
+# * CHANGELOG Unreleased (URL and header)
+version = "0.6.1"
+rust-version = "1.85"  # update MSRV in CI, and shield in README
diff --git a/README.md b/README.md
index 2957189f8c6..8b01d35d135 100644
--- a/README.md
+++ b/README.md
@@ -4,7 +4,7 @@
 [![stable-docs](https://img.shields.io/badge/docs-stable-blue)](https://docs.rs/stm32wlxx-hal/)
 [![nightly-docs](https://img.shields.io/badge/docs-nightly-black)](https://stm32-rs.github.io/stm32wlxx-hal/stm32wlxx_hal/index.html)
 [![crates.io](https://img.shields.io/crates/v/stm32wlxx-hal.svg)](https://crates.io/crates/stm32wlxx-hal)
-[![rustc](https://img.shields.io/badge/rustc-1.62+-blue.svg)](https://doc.rust-lang.org/cargo/reference/manifest.html#the-rust-version-field)
+[![rustc](https://img.shields.io/badge/rustc-1.85+-blue.svg)](https://doc.rust-lang.org/cargo/reference/manifest.html#the-rust-version-field)
 
 Embedded rust HAL (hardware abstraction layer) for the STM32WL series.
 
diff --git a/examples/Cargo.toml b/examples/Cargo.toml
index 34618b0479b..135a9a46c94 100644
--- a/examples/Cargo.toml
+++ b/examples/Cargo.toml
@@ -1,10 +1,13 @@
 [package]
 name = "examples"
-version = "0.1.0"
 publish = false
-authors = ["Alex Martens <alex@thinglab.org>"]
-edition = "2021"
-license = "MIT OR Apache-2.0"
+
+authors.workspace = true
+edition.workspace = true
+license.workspace = true
+repository.workspace = true
+rust-version.workspace = true
+version.workspace = true
 
 [dependencies]
 cortex-m = { version = "0.7", features = ["critical-section-single-core"] }
diff --git a/examples/examples/buzzer.rs b/examples/examples/buzzer.rs
index 10e69fc9d69..7172ef64698 100644
--- a/examples/examples/buzzer.rs
+++ b/examples/examples/buzzer.rs
@@ -12,7 +12,7 @@ use panic_probe as _; // panic handler
 use stm32wlxx_hal::{
     self as hal,
     cortex_m::{self, delay::Delay},
-    gpio::{pins, Output, PinState, PortA},
+    gpio::{Output, PinState, PortA, pins},
     pac,
     util::new_delay,
 };
diff --git a/examples/examples/gpio-blink.rs b/examples/examples/gpio-blink.rs
index f45126de33d..fa1f4ba3583 100644
--- a/examples/examples/gpio-blink.rs
+++ b/examples/examples/gpio-blink.rs
@@ -8,7 +8,7 @@ use panic_probe as _; // panic handler
 use stm32wlxx_hal::{
     self as hal,
     cortex_m::{self, delay::Delay},
-    gpio::{pins, Output, PinState, PortB},
+    gpio::{Output, PinState, PortB, pins},
     pac,
     util::new_delay,
 };
diff --git a/examples/examples/gpio-button-irq.rs b/examples/examples/gpio-button-irq.rs
index 8da55fa5c9c..7010bdeecf5 100644
--- a/examples/examples/gpio-button-irq.rs
+++ b/examples/examples/gpio-button-irq.rs
@@ -7,7 +7,7 @@ use defmt_rtt as _; // global logger
 use panic_probe as _; // panic handler
 use stm32wlxx_hal::{
     self as hal, cortex_m,
-    gpio::{pins, Exti, ExtiTrg, Input, PortC, Pull},
+    gpio::{Exti, ExtiTrg, Input, PortC, Pull, pins},
     pac::{self, interrupt},
 };
 
diff --git a/examples/examples/gpio-button.rs b/examples/examples/gpio-button.rs
index 46c4efe97c1..b23af2c793c 100644
--- a/examples/examples/gpio-button.rs
+++ b/examples/examples/gpio-button.rs
@@ -7,7 +7,7 @@ use defmt_rtt as _; // global logger
 use panic_probe as _; // panic handler
 use stm32wlxx_hal::{
     self as hal, cortex_m,
-    gpio::{pins, Input, PinState, PortC, Pull},
+    gpio::{Input, PinState, PortC, Pull, pins},
     pac,
 };
 
diff --git a/hal/Cargo.toml b/hal/Cargo.toml
index 1001f17a4e9..6bf63deb484 100644
--- a/hal/Cargo.toml
+++ b/hal/Cargo.toml
@@ -2,22 +2,15 @@
 name = "stm32wlxx-hal"
 description = "Hardware abstraction layer for the STM32WL series microcontrollers."
 readme = "../README.md"
-
-# To update version change:
-# * BSP versions
-# * BSP HAL dependency versions
-# * README
-# * BSP READMES
-# * lock file
-# * CHANGELOG Unreleased (URL and header)
-version = "0.6.1"
-authors = ["Alex Martens <alex@thinglab.org>"]
-edition = "2021"
-rust-version = "1.62"  # update MSRV in CI, BSPs, and shield in README
-license = "MIT OR Apache-2.0"
 keywords = ["arm", "cortex-m", "stm32", "hal"]
 categories = ["embedded", "hardware-support", "no-std"]
-repository = "https://github.com/stm32-rs/stm32wlxx-hal"
+
+authors.workspace = true
+edition.workspace = true
+license.workspace = true
+repository.workspace = true
+rust-version.workspace = true
+version.workspace = true
 
 [features]
 stm32wl5x_cm0p = ["stm32wl/stm32wl5x_cm0p"]
diff --git a/hal/src/adc.rs b/hal/src/adc.rs
index 6f20f1cc96a..d9c920b2b41 100644
--- a/hal/src/adc.rs
+++ b/hal/src/adc.rs
@@ -12,8 +12,8 @@
 #[cfg(not(feature = "stm32wl5x_cm0p"))]
 pub use pac::adc::cfgr2::{OVSR_A as OversampleRatio, OVSS_A as OversampleShift};
 
-use crate::gpio;
 use crate::Ratio;
+use crate::gpio;
 
 use super::pac;
 use core::{ptr::read_volatile, time::Duration};
@@ -522,8 +522,10 @@ impl Adc {
     /// [`new`]: Adc::new
     #[inline]
     pub unsafe fn steal() -> Adc {
-        Adc {
-            adc: pac::Peripherals::steal().ADC,
+        unsafe {
+            Adc {
+                adc: pac::Peripherals::steal().ADC,
+            }
         }
     }
 
@@ -712,7 +714,7 @@ impl Adc {
     #[cfg(feature = "rt")]
     #[inline]
     pub unsafe fn unmask_irq() {
-        pac::NVIC::unmask(pac::Interrupt::ADC)
+        unsafe { pac::NVIC::unmask(pac::Interrupt::ADC) }
     }
 
     /// Mask the ADC IRQ in the NVIC.
@@ -1294,7 +1296,7 @@ impl Adc {
     /// ```no_run
     /// use stm32wlxx_hal::{
     ///     adc::{self, Adc},
-    ///     gpio::{pins::B4, Analog, PortB},
+    ///     gpio::{Analog, PortB, pins::B4},
     ///     pac, rcc,
     ///     util::new_delay,
     /// };
diff --git a/hal/src/aes.rs b/hal/src/aes.rs
index 91137d3bc70..e1b3a9d87b3 100644
--- a/hal/src/aes.rs
+++ b/hal/src/aes.rs
@@ -312,10 +312,12 @@ impl Aes {
     /// [`new`]: Aes::new
     #[inline]
     pub unsafe fn steal() -> Aes {
-        let dp: pac::Peripherals = pac::Peripherals::steal();
-        Aes {
-            aes: dp.AES,
-            swap_mode: SwapMode::None,
+        unsafe {
+            let dp: pac::Peripherals = pac::Peripherals::steal();
+            Aes {
+                aes: dp.AES,
+                swap_mode: SwapMode::None,
+            }
         }
     }
 
@@ -334,7 +336,7 @@ impl Aes {
     #[cfg(all(not(feature = "stm32wl5x_cm0p"), feature = "rt"))]
     #[inline]
     pub unsafe fn unmask_irq() {
-        pac::NVIC::unmask(pac::Interrupt::AES)
+        unsafe { pac::NVIC::unmask(pac::Interrupt::AES) }
     }
 
     fn set_key(&mut self, key: &[u32]) -> KeySize {
@@ -417,7 +419,7 @@ impl Aes {
             self.aes.dinr.write(|w| w.din().bits(din));
         }
 
-        let remain_dw: usize = 4 - ((block.len() + 3) / 4);
+        let remain_dw: usize = 4 - block.len().div_ceil(4);
         for _ in 0..remain_dw {
             self.aes.dinr.write(|w| w.din().bits(0));
         }
@@ -441,7 +443,7 @@ impl Aes {
             }
         }
 
-        let remain_dw: usize = 4 - ((block.len() + 3) / 4);
+        let remain_dw: usize = 4 - block.len().div_ceil(4);
         for _ in 0..remain_dw {
             let _: u32 = self.aes.doutr.read().bits();
         }
diff --git a/hal/src/dac.rs b/hal/src/dac.rs
index d601108f6dd..999010277ee 100644
--- a/hal/src/dac.rs
+++ b/hal/src/dac.rs
@@ -2,7 +2,7 @@
 
 use super::pac;
 
-use crate::gpio::{pins::A10, Analog};
+use crate::gpio::{Analog, pins::A10};
 use pac::dac::mcr::MODE1_A;
 
 /// ADC modes that use the A10 output pin
@@ -133,10 +133,12 @@ impl Dac {
     ///
     /// [`new`]: Dac::new
     pub unsafe fn steal() -> Dac {
-        let dp: pac::Peripherals = pac::Peripherals::steal();
-        Dac {
-            dac: dp.DAC,
-            out: None,
+        unsafe {
+            let dp: pac::Peripherals = pac::Peripherals::steal();
+            Dac {
+                dac: dp.DAC,
+                out: None,
+            }
         }
     }
 
@@ -171,7 +173,7 @@ impl Dac {
     /// ```
     #[cfg(all(not(feature = "stm32wl5x_cm0p"), feature = "rt"))]
     pub unsafe fn unmask_irq() {
-        pac::NVIC::unmask(pac::Interrupt::DAC)
+        unsafe { pac::NVIC::unmask(pac::Interrupt::DAC) }
     }
 
     /// Mask the DAC interrupt.
@@ -345,7 +347,7 @@ impl Dac {
     /// ```no_run
     /// use stm32wlxx_hal::{
     ///     dac::{Dac, ModeChip, ModePin},
-    ///     gpio::{pins, Analog, PortA},
+    ///     gpio::{Analog, PortA, pins},
     ///     pac,
     /// };
     ///
diff --git a/hal/src/dma/cr.rs b/hal/src/dma/cr.rs
index 35340464f54..63bb017ee0a 100644
--- a/hal/src/dma/cr.rs
+++ b/hal/src/dma/cr.rs
@@ -803,11 +803,7 @@ impl Cr {
     /// ```
     #[must_use = "set_enable returns a modified Cr"]
     pub const fn set_enable(self, en: bool) -> Cr {
-        if en {
-            self.enable()
-        } else {
-            self.disable()
-        }
+        if en { self.enable() } else { self.disable() }
     }
 
     /// Enable the DMA peripheral.
diff --git a/hal/src/dma/mod.rs b/hal/src/dma/mod.rs
index 2c509fc3f3a..0333ab53b84 100644
--- a/hal/src/dma/mod.rs
+++ b/hal/src/dma/mod.rs
@@ -166,7 +166,7 @@ pub trait DmaCh: sealed::DmaOps {
     /// Check if the transfer is complete.
     ///
     /// ```no_run
-    /// use stm32wlxx_hal::dma::{flags, DmaCh};
+    /// use stm32wlxx_hal::dma::{DmaCh, flags};
     ///
     /// # let dma = unsafe { stm32wlxx_hal::dma::AllDma::steal().d1.c1 };
     /// let xfer_cpl: bool = dma.flags() & flags::XFER_CPL != 0;
@@ -182,7 +182,7 @@ pub trait DmaCh: sealed::DmaOps {
     /// Check and clear all set flags.
     ///
     /// ```no_run
-    /// use stm32wlxx_hal::dma::{flags, DmaCh};
+    /// use stm32wlxx_hal::dma::{DmaCh, flags};
     ///
     /// # let mut dma = unsafe { stm32wlxx_hal::dma::AllDma::steal().d1.c1 };
     /// let flags: u8 = dma.flags();
@@ -214,7 +214,7 @@ pub trait DmaCh: sealed::DmaOps {
     ///   DMAMUX1 overrun interrupt (C2IMR2\[15\])
     #[inline]
     unsafe fn unmask_irq(&self) {
-        pac::NVIC::unmask(Self::IRQ)
+        unsafe { pac::NVIC::unmask(Self::IRQ) }
     }
 
     /// Mask the DMA interrupt in the NVIC.
diff --git a/hal/src/flash.rs b/hal/src/flash.rs
index 29ca4db1436..d76846bed95 100644
--- a/hal/src/flash.rs
+++ b/hal/src/flash.rs
@@ -578,37 +578,39 @@ impl<'a> Flash<'a> {
     /// # Ok::<(), stm32wlxx_hal::flash::Error>(())
     /// ```
     pub unsafe fn program_bytes(&mut self, from: &[u8], to: AlignedAddr) -> Result<(), Error> {
-        if from.is_empty() {
-            return Ok(());
-        }
+        unsafe {
+            if from.is_empty() {
+                return Ok(());
+            }
 
-        if !flash_range().contains(&usize::from(to).saturating_add(from.len())) {
-            return Err(Error::Overflow);
-        }
+            if !flash_range().contains(&usize::from(to).saturating_add(from.len())) {
+                return Err(Error::Overflow);
+            }
 
-        let chunks_exact: ChunksExact<u8> = from.chunks_exact(8);
-        let remainder: &[u8] = chunks_exact.remainder();
-        let remainder_len: usize = remainder.len();
+            let chunks_exact: ChunksExact<u8> = from.chunks_exact(8);
+            let remainder: &[u8] = chunks_exact.remainder();
+            let remainder_len: usize = remainder.len();
 
-        let last_u64: u64 = chunks_exact
-            .remainder()
-            .iter()
-            .enumerate()
-            .fold(0, |acc, (n, byte)| acc | u64::from(*byte) << (8 * n));
+            let last_u64: u64 = chunks_exact
+                .remainder()
+                .iter()
+                .enumerate()
+                .fold(0, |acc, (n, byte)| acc | u64::from(*byte) << (8 * n));
 
-        for (n, chunk) in chunks_exact.enumerate() {
-            let chunk_u64: u64 = u64::from_le_bytes(chunk.try_into().unwrap());
-            let addr: usize = n * size_of::<u64>() + usize::from(to);
+            for (n, chunk) in chunks_exact.enumerate() {
+                let chunk_u64: u64 = u64::from_le_bytes(chunk.try_into().unwrap());
+                let addr: usize = n * size_of::<u64>() + usize::from(to);
 
-            self.standard_program(&chunk_u64, addr as *mut u64)?;
-        }
+                self.standard_program(&chunk_u64, addr as *mut u64)?;
+            }
 
-        if remainder_len != 0 {
-            let last_addr: usize = (usize::from(to) + from.len()).prev_multiple_of(&8);
-            self.standard_program(&last_u64, last_addr as *mut u64)?;
-        }
+            if remainder_len != 0 {
+                let last_addr: usize = (usize::from(to) + from.len()).prev_multiple_of(&8);
+                self.standard_program(&last_u64, last_addr as *mut u64)?;
+            }
 
-        Ok(())
+            Ok(())
+        }
     }
 
     /// Program a user-defined type.
@@ -625,71 +627,73 @@ impl<'a> Flash<'a> {
         from: *const T,
         to: *mut T,
     ) -> Result<(), Error> {
-        let size: isize = size_of::<T>() as isize;
-        if size == 0 {
-            return Ok(());
-        }
-
-        if !flash_range().contains(&(size_of::<T>() + to as usize)) {
-            return Err(Error::Overflow);
-        }
+        unsafe {
+            let size: isize = size_of::<T>() as isize;
+            if size == 0 {
+                return Ok(());
+            }
 
-        let sr: u32 = self.sr();
-        if sr & flags::BSY != 0 {
-            return Err(Error::Busy);
-        }
-        if sr & flags::PESD != 0 {
-            return Err(Error::Suspend);
-        }
+            if !flash_range().contains(&(size_of::<T>() + to as usize)) {
+                return Err(Error::Overflow);
+            }
 
-        self.clear_all_err();
+            let sr: u32 = self.sr();
+            if sr & flags::BSY != 0 {
+                return Err(Error::Busy);
+            }
+            if sr & flags::PESD != 0 {
+                return Err(Error::Suspend);
+            }
 
-        c1_c2!(
-            self.flash.cr.modify(|_, w| w.pg().set_bit()),
-            self.flash.c2cr.modify(|_, w| w.pg().set_bit())
-        );
+            self.clear_all_err();
 
-        // Calculate the index of the last double word
-        #[allow(unstable_name_collisions)]
-        let last_double_word_idx: isize = size.div_ceil(&8) - 1;
+            c1_c2!(
+                self.flash.cr.modify(|_, w| w.pg().set_bit()),
+                self.flash.c2cr.modify(|_, w| w.pg().set_bit())
+            );
 
-        // Write the type as double words and return the number of bytes written
-        let written_bytes: isize = (0..last_double_word_idx).fold(0, |acc, n| {
+            // Calculate the index of the last double word
+            #[allow(unstable_name_collisions)]
+            let last_double_word_idx: isize = size.div_ceil(&8) - 1;
+
+            // Write the type as double words and return the number of bytes written
+            let written_bytes: isize = (0..last_double_word_idx).fold(0, |acc, n| {
+                unsafe {
+                    write_volatile(
+                        (to as *mut u64).offset(n),
+                        (from as *const u64).offset(n).read(),
+                    )
+                };
+                acc + 8
+            });
+
+            // Determine how many bytes are left to write
+            let bytes_left: isize = size - written_bytes;
+
+            // Append the left over bytes to a double word,
+            // the last few bytes can look random in flash memory since Rust uses memory alignment to make accessing faster.
+            let last_double_word: u64 = (0..bytes_left).fold(0, |dw, n| {
+                let byte: u8 = (from as *const u8).offset(written_bytes + n).read();
+                dw | u64::from(byte) << (8 * n)
+            });
+
+            // Write the last double word
             unsafe {
                 write_volatile(
-                    (to as *mut u64).offset(n),
-                    (from as *const u64).offset(n).read(),
+                    (to as *mut u64).offset(last_double_word_idx),
+                    (&last_double_word as *const u64).read(),
                 )
             };
-            acc + 8
-        });
-
-        // Determine how many bytes are left to write
-        let bytes_left: isize = size - written_bytes;
 
-        // Append the left over bytes to a double word,
-        // the last few bytes can look random in flash memory since Rust uses memory alignment to make accessing faster.
-        let last_double_word: u64 = (0..bytes_left).fold(0, |dw, n| {
-            let byte: u8 = (from as *const u8).offset(written_bytes + n).read();
-            dw | u64::from(byte) << (8 * n)
-        });
+            let ret: Result<(), Error> = self.wait_for_not_busy();
 
-        // Write the last double word
-        unsafe {
-            write_volatile(
-                (to as *mut u64).offset(last_double_word_idx),
-                (&last_double_word as *const u64).read(),
-            )
-        };
-
-        let ret: Result<(), Error> = self.wait_for_not_busy();
-
-        c1_c2!(
-            self.flash.cr.modify(|_, w| w.pg().clear_bit()),
-            self.flash.c2cr.modify(|_, w| w.pg().clear_bit())
-        );
+            c1_c2!(
+                self.flash.cr.modify(|_, w| w.pg().clear_bit()),
+                self.flash.c2cr.modify(|_, w| w.pg().clear_bit())
+            );
 
-        ret
+            ret
+        }
     }
 
     /// Program 256 bytes.
@@ -705,7 +709,7 @@ impl<'a> Flash<'a> {
     ///    The compiler may inline this function, because `#[inline(never)]` is
     ///    merely a suggestion.
     #[allow(unused_unsafe)]
-    #[cfg_attr(target_os = "none", link_section = ".data")]
+    #[cfg_attr(target_os = "none", unsafe(link_section = ".data"))]
     #[inline(never)]
     pub unsafe fn fast_program(&mut self, from: *const u64, to: *mut u64) -> Result<(), Error> {
         let sr: u32 = self.sr();
@@ -808,7 +812,7 @@ impl<'a> Flash<'a> {
     /// 1. The CPU must execute this from SRAM.
     ///    The compiler may inline this function, because `#[inline(never)]` is
     ///    merely a suggestion.
-    #[cfg_attr(target_os = "none", link_section = ".data")]
+    #[cfg_attr(target_os = "none", unsafe(link_section = ".data"))]
     #[inline(never)]
     pub unsafe fn mass_erase(&mut self) -> Result<(), Error> {
         let sr: u32 = self.sr();
diff --git a/hal/src/gpio.rs b/hal/src/gpio.rs
index 085db957866..64649aeb556 100644
--- a/hal/src/gpio.rs
+++ b/hal/src/gpio.rs
@@ -173,7 +173,7 @@ impl<const BASE: usize, const N: u8> Pin<BASE, N> {
 }
 
 pub(crate) mod sealed {
-    use super::{adc, CriticalSection, OutputType, PinState, Pull, Speed};
+    use super::{CriticalSection, OutputType, PinState, Pull, Speed, adc};
 
     /// GPIO modes.
     #[repr(u8)]
@@ -304,7 +304,7 @@ pub trait Exti {
     ///
     /// ```no_run
     /// use stm32wlxx_hal::{
-    ///     gpio::{pins::C6, Exti},
+    ///     gpio::{Exti, pins::C6},
     ///     pac,
     /// };
     ///
@@ -321,7 +321,7 @@ pub trait Exti {
     ///
     /// ```no_run
     /// use stm32wlxx_hal::{
-    ///     gpio::{pins::C6, Exti},
+    ///     gpio::{Exti, pins::C6},
     ///     pac,
     /// };
     ///
@@ -339,7 +339,7 @@ pub trait Exti {
     ///
     /// ```no_run
     /// use stm32wlxx_hal::{
-    ///     gpio::{pins::C6, Exti},
+    ///     gpio::{Exti, pins::C6},
     ///     pac,
     /// };
     ///
@@ -360,7 +360,7 @@ pub trait Exti {
     ///
     /// ```no_run
     /// use stm32wlxx_hal::{
-    ///     gpio::{pins::C6, Exti},
+    ///     gpio::{Exti, pins::C6},
     ///     pac,
     /// };
     ///
@@ -402,7 +402,7 @@ pub trait Exti {
     ///
     /// ```no_run
     /// use stm32wlxx_hal::{
-    ///     gpio::{pins::C6, Exti, ExtiTrg},
+    ///     gpio::{Exti, ExtiTrg, pins::C6},
     ///     pac,
     /// };
     ///
@@ -431,7 +431,7 @@ pub trait Exti {
     ///
     /// ```no_run
     /// use stm32wlxx_hal::{
-    ///     gpio::{pins::C6, Exti, ExtiTrg},
+    ///     gpio::{Exti, ExtiTrg, pins::C6},
     ///     pac,
     /// };
     ///
@@ -441,7 +441,7 @@ pub trait Exti {
     /// ```
     #[inline]
     unsafe fn unmask() {
-        pac::NVIC::unmask(Self::INTERRUPT)
+        unsafe { pac::NVIC::unmask(Self::INTERRUPT) }
     }
 
     /// Mask the interrupt in the NVIC.
@@ -454,7 +454,7 @@ pub trait Exti {
     /// Mask C6 (which will mask all pins 5-9).
     ///
     /// ```no_run
-    /// use stm32wlxx_hal::gpio::{pins::C6, Exti};
+    /// use stm32wlxx_hal::gpio::{Exti, pins::C6};
     ///
     /// C6::mask();
     /// ```
@@ -467,8 +467,8 @@ pub trait Exti {
 /// GPIO pins
 pub mod pins {
     use super::{
-        adc, pac, CriticalSection, OutputType, Pin, PinState, Pull, Speed, GPIOA_BASE, GPIOB_BASE,
-        GPIOC_BASE,
+        CriticalSection, GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, OutputType, Pin, PinState, Pull,
+        Speed, adc, pac,
     };
 
     macro_rules! gpio_struct {
@@ -897,7 +897,7 @@ impl PortA {
     ///
     /// ```no_run
     /// use stm32wlxx_hal::{
-    ///     gpio::{pins, PortA},
+    ///     gpio::{PortA, pins},
     ///     pac,
     /// };
     ///
@@ -1041,7 +1041,7 @@ impl PortB {
     ///
     /// ```no_run
     /// use stm32wlxx_hal::{
-    ///     gpio::{pins, PortB},
+    ///     gpio::{PortB, pins},
     ///     pac,
     /// };
     ///
@@ -1173,7 +1173,7 @@ impl PortC {
     ///
     /// ```no_run
     /// use stm32wlxx_hal::{
-    ///     gpio::{pins, PortC},
+    ///     gpio::{PortC, pins},
     ///     pac,
     /// };
     ///
@@ -1330,7 +1330,7 @@ where
     ///
     /// ```no_run
     /// use stm32wlxx_hal::{
-    ///     gpio::{self, pins, Output, PortC},
+    ///     gpio::{self, Output, PortC, pins},
     ///     pac,
     /// };
     ///
@@ -1374,7 +1374,7 @@ where
     ///
     /// ```no_run
     /// use stm32wlxx_hal::{
-    ///     gpio::{pins, Output, OutputArgs, PortC},
+    ///     gpio::{Output, OutputArgs, PortC, pins},
     ///     pac,
     /// };
     ///
@@ -1401,7 +1401,7 @@ where
     /// # Example
     ///
     /// ```
-    /// use stm32wlxx_hal::gpio::{pins, Output};
+    /// use stm32wlxx_hal::gpio::{Output, pins};
     ///
     /// // ... setup occurs here
     ///
@@ -1409,7 +1409,7 @@ where
     /// ```
     #[inline]
     pub unsafe fn steal() -> Self {
-        Output { pin: P::steal() }
+        unsafe { Output { pin: P::steal() } }
     }
 
     /// Free the GPIO pin.
@@ -1420,7 +1420,7 @@ where
     ///
     /// ```no_run
     /// use stm32wlxx_hal::{
-    ///     gpio::{pins, Output, PortC},
+    ///     gpio::{Output, PortC, pins},
     ///     pac,
     /// };
     ///
@@ -1446,7 +1446,7 @@ where
     ///
     /// ```no_run
     /// use stm32wlxx_hal::{
-    ///     gpio::{pins, Output, PinState, PortC},
+    ///     gpio::{Output, PinState, PortC, pins},
     ///     pac,
     /// };
     ///
@@ -1473,7 +1473,7 @@ where
     ///
     /// ```no_run
     /// use stm32wlxx_hal::{
-    ///     gpio::{pins, Output, PortC},
+    ///     gpio::{Output, PortC, pins},
     ///     pac,
     /// };
     ///
@@ -1499,7 +1499,7 @@ where
     ///
     /// ```no_run
     /// use stm32wlxx_hal::{
-    ///     gpio::{pins, Output, PortC},
+    ///     gpio::{Output, PortC, pins},
     ///     pac,
     /// };
     ///
@@ -1523,7 +1523,7 @@ where
     /// ```no_run
     /// use core::ops::Not;
     /// use stm32wlxx_hal::{
-    ///     gpio::{pins, Output, PinState, PortC},
+    ///     gpio::{Output, PinState, PortC, pins},
     ///     pac,
     /// };
     ///
@@ -1595,7 +1595,7 @@ where
     ///
     /// ```no_run
     /// use stm32wlxx_hal::{
-    ///     gpio::{pins, Input, PortC, Pull},
+    ///     gpio::{Input, PortC, Pull, pins},
     ///     pac,
     /// };
     ///
@@ -1620,7 +1620,7 @@ where
     ///
     /// ```no_run
     /// use stm32wlxx_hal::{
-    ///     gpio::{pins, Input, PortC},
+    ///     gpio::{Input, PortC, pins},
     ///     pac,
     /// };
     ///
@@ -1646,7 +1646,7 @@ where
     /// # Example
     ///
     /// ```
-    /// use stm32wlxx_hal::gpio::{pins, Input};
+    /// use stm32wlxx_hal::gpio::{Input, pins};
     ///
     /// // ... setup occurs here
     ///
@@ -1654,7 +1654,7 @@ where
     /// ```
     #[inline]
     pub unsafe fn steal() -> Self {
-        Input { pin: P::steal() }
+        unsafe { Input { pin: P::steal() } }
     }
 
     /// Free the GPIO pin.
@@ -1665,7 +1665,7 @@ where
     ///
     /// ```no_run
     /// use stm32wlxx_hal::{
-    ///     gpio::{pins, Input, PortC},
+    ///     gpio::{Input, PortC, pins},
     ///     pac,
     /// };
     ///
@@ -1689,7 +1689,7 @@ where
     ///
     /// ```no_run
     /// use stm32wlxx_hal::{
-    ///     gpio::{pins, Input, PinState, PortC, Pull},
+    ///     gpio::{Input, PinState, PortC, Pull, pins},
     ///     pac,
     /// };
     ///
@@ -1746,7 +1746,7 @@ where
     ///
     /// ```no_run
     /// use stm32wlxx_hal::{
-    ///     gpio::{pins, Analog, PortB},
+    ///     gpio::{Analog, PortB, pins},
     ///     pac,
     /// };
     ///
@@ -1768,7 +1768,7 @@ where
     ///
     /// ```no_run
     /// use stm32wlxx_hal::{
-    ///     gpio::{pins, Analog, PortB},
+    ///     gpio::{Analog, PortB, pins},
     ///     pac,
     /// };
     ///
@@ -1819,7 +1819,7 @@ impl RfBusy {
     ///
     /// ```no_run
     /// use stm32wlxx_hal::{
-    ///     gpio::{pins, PortA, RfBusy},
+    ///     gpio::{PortA, RfBusy, pins},
     ///     pac,
     /// };
     ///
@@ -1871,7 +1871,7 @@ impl RfIrq0 {
     ///
     /// ```no_run
     /// use stm32wlxx_hal::{
-    ///     gpio::{pins, PortB, RfIrq0},
+    ///     gpio::{PortB, RfIrq0, pins},
     ///     pac,
     /// };
     ///
@@ -1923,7 +1923,7 @@ impl RfIrq1 {
     ///
     /// ```no_run
     /// use stm32wlxx_hal::{
-    ///     gpio::{pins, PortB, RfIrq1},
+    ///     gpio::{PortB, RfIrq1, pins},
     ///     pac,
     /// };
     ///
@@ -1975,7 +1975,7 @@ impl RfIrq2 {
     ///
     /// ```no_run
     /// use stm32wlxx_hal::{
-    ///     gpio::{pins, PortB, RfIrq2},
+    ///     gpio::{PortB, RfIrq2, pins},
     ///     pac,
     /// };
     ///
@@ -2005,7 +2005,7 @@ impl RfNssDbg {
     ///
     /// ```no_run
     /// use stm32wlxx_hal::{
-    ///     gpio::{pins, PortA, RfNssDbg},
+    ///     gpio::{PortA, RfNssDbg, pins},
     ///     pac,
     /// };
     ///
@@ -2027,7 +2027,7 @@ impl RfNssDbg {
     ///
     /// ```no_run
     /// use stm32wlxx_hal::{
-    ///     gpio::{pins, PortA, RfNssDbg},
+    ///     gpio::{PortA, RfNssDbg, pins},
     ///     pac,
     /// };
     ///
@@ -2057,7 +2057,7 @@ impl SgSckDbg {
     ///
     /// ```no_run
     /// use stm32wlxx_hal::{
-    ///     gpio::{pins, PortA, SgSckDbg},
+    ///     gpio::{PortA, SgSckDbg, pins},
     ///     pac,
     /// };
     ///
@@ -2079,7 +2079,7 @@ impl SgSckDbg {
     ///
     /// ```no_run
     /// use stm32wlxx_hal::{
-    ///     gpio::{pins, PortA, SgSckDbg},
+    ///     gpio::{PortA, SgSckDbg, pins},
     ///     pac,
     /// };
     ///
@@ -2109,7 +2109,7 @@ impl SgMisoDbg {
     ///
     /// ```no_run
     /// use stm32wlxx_hal::{
-    ///     gpio::{pins, PortA, SgMisoDbg},
+    ///     gpio::{PortA, SgMisoDbg, pins},
     ///     pac,
     /// };
     ///
@@ -2131,7 +2131,7 @@ impl SgMisoDbg {
     ///
     /// ```no_run
     /// use stm32wlxx_hal::{
-    ///     gpio::{pins, PortA, SgMisoDbg},
+    ///     gpio::{PortA, SgMisoDbg, pins},
     ///     pac,
     /// };
     ///
@@ -2162,7 +2162,7 @@ impl SgMosiDbg {
     /// ```no_run
     /// use stm32wlxx_hal::{
     ///     cortex_m,
-    ///     gpio::{pins, PortA, SgMosiDbg},
+    ///     gpio::{PortA, SgMosiDbg, pins},
     ///     pac,
     /// };
     ///
@@ -2185,7 +2185,7 @@ impl SgMosiDbg {
     /// ```no_run
     /// use stm32wlxx_hal::{
     ///     cortex_m,
-    ///     gpio::{pins, PortA, SgMosiDbg},
+    ///     gpio::{PortA, SgMosiDbg, pins},
     ///     pac,
     /// };
     ///
diff --git a/hal/src/i2c.rs b/hal/src/i2c.rs
index b3878e7ed94..b42606f4fca 100644
--- a/hal/src/i2c.rs
+++ b/hal/src/i2c.rs
@@ -3,7 +3,7 @@
 use crate::{
     embedded_hal::blocking::i2c::{Read, Write, WriteRead},
     gpio::{OutputType, Pull},
-    pac::{self, rcc::ccipr::I2C3SEL_A, I2C1, I2C2, I2C3, RCC},
+    pac::{self, I2C1, I2C2, I2C3, RCC, rcc::ccipr::I2C3SEL_A},
     rcc::{pclk1_hz, sysclk_hz},
 };
 
diff --git a/hal/src/lptim/cr.rs b/hal/src/lptim/cr.rs
index 01f80b3d616..b8c08c0009f 100644
--- a/hal/src/lptim/cr.rs
+++ b/hal/src/lptim/cr.rs
@@ -101,11 +101,7 @@ impl Cr {
     /// ```
     #[must_use = "set_enable returns a modified Cr"]
     pub const fn set_enable(self, en: bool) -> Cr {
-        if en {
-            self.enable()
-        } else {
-            self.disable()
-        }
+        if en { self.enable() } else { self.disable() }
     }
 
     /// Enable the LPTIM peripheral.
diff --git a/hal/src/lptim/mod.rs b/hal/src/lptim/mod.rs
index 434e1d8df8a..e7142d03ae8 100644
--- a/hal/src/lptim/mod.rs
+++ b/hal/src/lptim/mod.rs
@@ -35,11 +35,12 @@ use cortex_m::interrupt::CriticalSection;
 pub use cr::Cr;
 
 use crate::{
+    Ratio,
     gpio::{
         pins,
         sealed::{LpTim1Etr, LpTim1Out, LpTim2Etr, LpTim2Out, LpTim3Etr, LpTim3Out},
     },
-    pac, Ratio,
+    pac,
 };
 use core::cmp::min;
 use paste::paste;
@@ -197,7 +198,7 @@ macro_rules! impl_lptim_base_for {
             /// is set.
             #[inline(always)]
             unsafe fn cnt() -> u16 {
-                (*pac::$lptim::PTR).cnt.read().cnt().bits()
+                unsafe { (*pac::$lptim::PTR).cnt.read().cnt().bits() }
             }
 
             #[inline(always)]
diff --git a/hal/src/pka.rs b/hal/src/pka.rs
index 5a2d94098cf..164286f607a 100644
--- a/hal/src/pka.rs
+++ b/hal/src/pka.rs
@@ -317,8 +317,10 @@ impl Pka {
     ///
     /// [`new`]: Pka::new
     pub unsafe fn steal() -> Pka {
-        Pka {
-            pka: pac::Peripherals::steal().PKA,
+        unsafe {
+            Pka {
+                pka: pac::Peripherals::steal().PKA,
+            }
         }
     }
 
@@ -372,7 +374,7 @@ impl Pka {
     #[cfg(all(not(feature = "stm32wl5x_cm0p"), feature = "rt"))]
     #[inline]
     pub unsafe fn unmask_irq() {
-        pac::NVIC::unmask(pac::Interrupt::PKA)
+        unsafe { pac::NVIC::unmask(pac::Interrupt::PKA) }
     }
 
     #[inline]
@@ -390,21 +392,25 @@ impl Pka {
     }
 
     unsafe fn write_ram(&mut self, offset: usize, buf: &[u32]) {
-        // asserts are for internal correctness, should not be accessible by users
-        debug_assert_eq!(offset % 4, 0);
-        debug_assert!(offset + core::mem::size_of_val(buf) < 0x5800_33FF);
-        buf.iter().rev().enumerate().for_each(|(idx, &dw)| {
-            write_volatile((offset + idx * size_of::<u32>()) as *mut u32, dw)
-        });
+        unsafe {
+            // asserts are for internal correctness, should not be accessible by users
+            debug_assert_eq!(offset % 4, 0);
+            debug_assert!(offset + core::mem::size_of_val(buf) < 0x5800_33FF);
+            buf.iter().rev().enumerate().for_each(|(idx, &dw)| {
+                write_volatile((offset + idx * size_of::<u32>()) as *mut u32, dw)
+            });
+        }
     }
 
     unsafe fn read_ram(&mut self, offset: usize, buf: &mut [u32]) {
-        // asserts are for internal correctness, should not be accessible by users
-        debug_assert_eq!(offset % 4, 0);
-        debug_assert!(offset + core::mem::size_of_val(buf) < 0x5800_33FF);
-        buf.iter_mut().rev().enumerate().for_each(|(idx, dw)| {
-            *dw = read_volatile((offset + idx * size_of::<u32>()) as *const u32);
-        });
+        unsafe {
+            // asserts are for internal correctness, should not be accessible by users
+            debug_assert_eq!(offset % 4, 0);
+            debug_assert!(offset + core::mem::size_of_val(buf) < 0x5800_33FF);
+            buf.iter_mut().rev().enumerate().for_each(|(idx, dw)| {
+                *dw = read_volatile((offset + idx * size_of::<u32>()) as *const u32);
+            });
+        }
     }
 
     #[inline]
diff --git a/hal/src/pwr.rs b/hal/src/pwr.rs
index da5f525b62f..a26250c0c90 100644
--- a/hal/src/pwr.rs
+++ b/hal/src/pwr.rs
@@ -1,6 +1,6 @@
 //! Power control
 
-use core::sync::atomic::{compiler_fence, Ordering::SeqCst};
+use core::sync::atomic::{Ordering::SeqCst, compiler_fence};
 
 use cortex_m::interrupt::CriticalSection;
 
@@ -52,7 +52,7 @@ impl WakeupPin {
 /// ```no_run
 /// use stm32wlxx_hal::{
 ///     pac,
-///     pwr::{setup_wakeup_pins, WakeupPin},
+///     pwr::{WakeupPin, setup_wakeup_pins},
 /// };
 ///
 /// let mut dp: pac::Peripherals = pac::Peripherals::take().unwrap();
@@ -214,7 +214,7 @@ impl From<LprunRange> for MsiRange {
 /// ```no_run
 /// use stm32wlxx_hal::{
 ///     pac,
-///     pwr::{enter_lprun_msi, LprunRange},
+///     pwr::{LprunRange, enter_lprun_msi},
 /// };
 ///
 /// let mut dp: pac::Peripherals = pac::Peripherals::take().unwrap();
@@ -236,9 +236,11 @@ pub unsafe fn enter_lprun_msi(
     range: LprunRange,
     cs: &CriticalSection,
 ) {
-    crate::rcc::set_sysclk_msi(flash, pwr, rcc, range.into(), cs);
-    rcc.cr.modify(|_, w| w.hseon().disabled());
-    pwr.cr1.modify(|_, w| w.lpr().low_power_mode());
+    unsafe {
+        crate::rcc::set_sysclk_msi(flash, pwr, rcc, range.into(), cs);
+        rcc.cr.modify(|_, w| w.hseon().disabled());
+        pwr.cr1.modify(|_, w| w.lpr().low_power_mode());
+    }
 }
 
 /// Exit low-power run mode.
@@ -250,7 +252,7 @@ pub unsafe fn enter_lprun_msi(
 /// ```no_run
 /// use stm32wlxx_hal::{
 ///     pac,
-///     pwr::{enter_lprun_msi, exit_lprun, LprunRange},
+///     pwr::{LprunRange, enter_lprun_msi, exit_lprun},
 /// };
 ///
 /// let mut dp: pac::Peripherals = pac::Peripherals::take().unwrap();
diff --git a/hal/src/rcc.rs b/hal/src/rcc.rs
index 3d56605a29b..fc2fc3a8587 100644
--- a/hal/src/rcc.rs
+++ b/hal/src/rcc.rs
@@ -6,7 +6,7 @@
 //!
 //! Quickstart: [`set_sysclk_msi_max`]
 
-use crate::{pac, Ratio};
+use crate::{Ratio, pac};
 use cortex_m::{interrupt::CriticalSection, peripheral::syst::SystClkSource};
 
 use pac::flash::acr::LATENCY_A;
@@ -252,7 +252,7 @@ const fn ppre_div(pre: u8) -> u8 {
 /// ```no_run
 /// use stm32wlxx_hal::{
 ///     pac,
-///     rcc::{set_sysclk_hse, Vos},
+///     rcc::{Vos, set_sysclk_hse},
 /// };
 ///
 /// let mut dp: pac::Peripherals = pac::Peripherals::take().unwrap();
@@ -375,7 +375,7 @@ pub unsafe fn set_sysclk_hsi(
 /// ```no_run
 /// use stm32wlxx_hal::{
 ///     pac,
-///     rcc::{set_sysclk_msi, MsiRange},
+///     rcc::{MsiRange, set_sysclk_msi},
 /// };
 ///
 /// let mut dp: pac::Peripherals = pac::Peripherals::take().unwrap();
@@ -396,46 +396,48 @@ pub unsafe fn set_sysclk_msi(
     range: MsiRange,
     cs: &CriticalSection,
 ) {
-    // startup the MSI clock
-    rcc.cr.modify(|_, w| w.msion().enabled());
+    unsafe {
+        // startup the MSI clock
+        rcc.cr.modify(|_, w| w.msion().enabled());
 
-    let vos: Vos = range.vos();
+        let vos: Vos = range.vos();
 
-    // increase VOS range
-    if vos == Vos::V1_2 {
-        pwr.cr1.modify(|_, w| w.vos().v1_2());
-        while pwr.sr2.read().vosf().is_change() {}
-    }
+        // increase VOS range
+        if vos == Vos::V1_2 {
+            pwr.cr1.modify(|_, w| w.vos().v1_2());
+            while pwr.sr2.read().vosf().is_change() {}
+        }
 
-    let cfgr = rcc.cfgr.read();
-
-    // ES0500 Rev 3 erratum handling:
-    //
-    // A voltage drop to 1.08 V may occur on the 1.2 V regulated supply when the
-    // MSI frequency is changed as follows:
-    // * from MSI at 400 kHz to MSI at 24 MHz and above
-    // * from MSI at 1 MHZ to MSI at 48 MHz
-    // As a result, the voltage drop may cause CPU HardFault.
-    // To ensure there is no impact on the 1.2 V supply, introduce an
-    // intermediate MSI frequency
-    //
-    // Open question:
-    // Does this apply when the CPU is clocked by the PLL via MSI?
-    if cfgr.sws().is_msi() {
-        let current_range: MsiRange = MsiRange::from_rcc(rcc);
-
-        if ((current_range == MsiRange::Range400k) && (range >= MsiRange::Range24M))
-            || ((current_range == MsiRange::Range1M) && (range == MsiRange::Range48M))
-        {
-            set_sysclk_msi_inner(flash, rcc, MsiRange::Range16M, vos, cs)
+        let cfgr = rcc.cfgr.read();
+
+        // ES0500 Rev 3 erratum handling:
+        //
+        // A voltage drop to 1.08 V may occur on the 1.2 V regulated supply when the
+        // MSI frequency is changed as follows:
+        // * from MSI at 400 kHz to MSI at 24 MHz and above
+        // * from MSI at 1 MHZ to MSI at 48 MHz
+        // As a result, the voltage drop may cause CPU HardFault.
+        // To ensure there is no impact on the 1.2 V supply, introduce an
+        // intermediate MSI frequency
+        //
+        // Open question:
+        // Does this apply when the CPU is clocked by the PLL via MSI?
+        if cfgr.sws().is_msi() {
+            let current_range: MsiRange = MsiRange::from_rcc(rcc);
+
+            if ((current_range == MsiRange::Range400k) && (range >= MsiRange::Range24M))
+                || ((current_range == MsiRange::Range1M) && (range == MsiRange::Range48M))
+            {
+                set_sysclk_msi_inner(flash, rcc, MsiRange::Range16M, vos, cs)
+            }
         }
-    }
 
-    set_sysclk_msi_inner(flash, rcc, range, vos, cs);
+        set_sysclk_msi_inner(flash, rcc, range, vos, cs);
 
-    // decrease VOS range
-    if vos == Vos::V1_0 {
-        pwr.cr1.modify(|_, w| w.vos().v1_0());
+        // decrease VOS range
+        if vos == Vos::V1_0 {
+            pwr.cr1.modify(|_, w| w.vos().v1_0());
+        }
     }
 }
 
@@ -509,7 +511,7 @@ pub unsafe fn set_sysclk_msi_max(
     rcc: &mut pac::RCC,
     cs: &CriticalSection,
 ) {
-    set_sysclk_msi(flash, pwr, rcc, MsiRange::Range48M, cs)
+    unsafe { set_sysclk_msi(flash, pwr, rcc, MsiRange::Range48M, cs) }
 }
 
 #[cfg_attr(feature = "stm32wl5x_cm0p", allow(dead_code))]
@@ -898,7 +900,7 @@ pub fn lsi_hz(rcc: &pac::RCC) -> u16 {
 /// ```no_run
 /// use stm32wlxx_hal::{
 ///     pac,
-///     rcc::{setup_lsi, LsiPre},
+///     rcc::{LsiPre, setup_lsi},
 /// };
 ///
 /// let mut dp: pac::Peripherals = pac::Peripherals::take().unwrap();
@@ -1022,7 +1024,7 @@ impl Lsco {
     ///
     /// ```no_run
     /// use stm32wlxx_hal::{
-    ///     gpio::{pins, PortA},
+    ///     gpio::{PortA, pins},
     ///     pac,
     ///     rcc::{Lsco, LscoSel},
     /// };
diff --git a/hal/src/rng.rs b/hal/src/rng.rs
index 2ec796da25e..c8e838ac46b 100644
--- a/hal/src/rng.rs
+++ b/hal/src/rng.rs
@@ -167,10 +167,12 @@ impl Rng {
     /// [`new`]: Rng::new
     #[inline]
     pub unsafe fn steal() -> Rng {
-        let dp: pac::Peripherals = pac::Peripherals::steal();
-        Rng {
-            rng: dp.RNG,
-            err_cnt: 0,
+        unsafe {
+            let dp: pac::Peripherals = pac::Peripherals::steal();
+            Rng {
+                rng: dp.RNG,
+                err_cnt: 0,
+            }
         }
     }
 
@@ -189,7 +191,7 @@ impl Rng {
     #[cfg(all(not(feature = "stm32wl5x_cm0p"), feature = "rt"))]
     #[inline]
     pub unsafe fn unmask_irq() {
-        pac::NVIC::unmask(pac::Interrupt::TRUE_RNG)
+        unsafe { pac::NVIC::unmask(pac::Interrupt::TRUE_RNG) }
     }
 
     /// Disable the RNG clock.
diff --git a/hal/src/rtc/alarm.rs b/hal/src/rtc/alarm.rs
index 7b47f26f489..ff6e3416c9c 100644
--- a/hal/src/rtc/alarm.rs
+++ b/hal/src/rtc/alarm.rs
@@ -66,11 +66,7 @@ impl From<Alarm> for chrono::NaiveTime {
 }
 
 const fn const_min(a: u8, b: u8) -> u32 {
-    if a < b {
-        a as u32
-    } else {
-        b as u32
-    }
+    if a < b { a as u32 } else { b as u32 }
 }
 
 impl Default for Alarm {
diff --git a/hal/src/spi.rs b/hal/src/spi.rs
index 3c835d35471..7073c47bf47 100644
--- a/hal/src/spi.rs
+++ b/hal/src/spi.rs
@@ -37,7 +37,7 @@ use crate::{
 
 pub use embedded_hal::{
     blocking::spi::{Transfer, Write},
-    spi::{FullDuplex, Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3},
+    spi::{FullDuplex, MODE_0, MODE_1, MODE_2, MODE_3, Mode, Phase, Polarity},
 };
 
 use cortex_m::interrupt::CriticalSection;
@@ -158,7 +158,7 @@ pub(crate) mod sealed {
     };
     use core::{
         ptr::{read_volatile, write_volatile},
-        sync::atomic::{compiler_fence, Ordering::SeqCst},
+        sync::atomic::{Ordering::SeqCst, compiler_fence},
     };
 
     use pac::dmamux::c0cr::DMAREQ_ID_A::{
@@ -262,6 +262,7 @@ pub(crate) mod sealed {
                 .set_mem_inc(true)
                 .set_enable(true);
 
+            #[allow(static_mut_refs)]
             rx_dma.set_mem_addr(unsafe { GARBAGE.as_mut_ptr() } as u32);
             tx_dma.set_mem_addr(words.as_ptr() as u32);
 
@@ -1142,10 +1143,12 @@ impl Spi3<SgMiso, SgMosi> {
     }
 
     pub(crate) unsafe fn steal() -> Self {
-        Self {
-            spi: pac::Peripherals::steal().SPI3,
-            mosi: SgMosi::new(),
-            miso: SgMiso::new(),
+        unsafe {
+            Self {
+                spi: pac::Peripherals::steal().SPI3,
+                mosi: SgMosi::new(),
+                miso: SgMiso::new(),
+            }
         }
     }
 }
@@ -1199,10 +1202,12 @@ impl<MISODMA: DmaCh, MOSIDMA: DmaCh> Spi3<MISODMA, MOSIDMA> {
     }
 
     pub(crate) unsafe fn steal_with_dma(miso_dma: MISODMA, mosi_dma: MOSIDMA) -> Self {
-        Self {
-            spi: pac::Peripherals::steal().SPI3,
-            miso: miso_dma,
-            mosi: mosi_dma,
+        unsafe {
+            Self {
+                spi: pac::Peripherals::steal().SPI3,
+                miso: miso_dma,
+                mosi: mosi_dma,
+            }
         }
     }
 }
@@ -1217,7 +1222,7 @@ impl<SPI, SCK, MISO, MOSI> Spi<SPI, SCK, MISO, MOSI> {
     ///     dma::AllDma,
     ///     gpio::PortA,
     ///     pac,
-    ///     spi::{BaudRate::Div2, Spi, MODE_0},
+    ///     spi::{BaudRate::Div2, MODE_0, Spi},
     /// };
     ///
     /// let mut dp = pac::Peripherals::take().unwrap();
diff --git a/hal/src/subghz/mod.rs b/hal/src/subghz/mod.rs
index 3f39602ab4d..536156c7981 100644
--- a/hal/src/subghz/mod.rs
+++ b/hal/src/subghz/mod.rs
@@ -165,7 +165,7 @@ pub unsafe fn wakeup() {
 /// ```
 #[inline]
 pub unsafe fn unmask_irq() {
-    pac::NVIC::unmask(pac::Interrupt::RADIO_IRQ_BUSY)
+    unsafe { pac::NVIC::unmask(pac::Interrupt::RADIO_IRQ_BUSY) }
 }
 
 /// Mask the SubGHz IRQ in the NVIC.
@@ -371,7 +371,7 @@ impl<MISO, MOSI> SubGhz<MISO, MOSI> {
     /// 4. You are responsible for setting up anything that may have lost state
     ///    while the clock was disabled.
     pub unsafe fn disable_spi_clock(rcc: &mut pac::RCC) {
-        Spi3::<SgMiso, SgMosi>::disable_clock(rcc)
+        unsafe { Spi3::<SgMiso, SgMosi>::disable_clock(rcc) }
     }
 
     /// Enable the SPI3 (SubGHz SPI) clock.
@@ -522,7 +522,7 @@ impl SubGhz<SgMiso, SgMosi> {
     ///
     /// [`new`]: SubGhz::new
     pub unsafe fn steal() -> SubGhz<SgMiso, SgMosi> {
-        SubGhz { spi: Spi3::steal() }
+        unsafe { SubGhz { spi: Spi3::steal() } }
     }
 }
 
@@ -621,8 +621,10 @@ impl<MISO: DmaCh, MOSI: DmaCh> SubGhz<MISO, MOSI> {
     ///
     /// [`new_with_dma`]: SubGhz::new_with_dma
     pub unsafe fn steal_with_dma(miso_dma: MISO, mosi_dma: MOSI) -> Self {
-        SubGhz {
-            spi: Spi3::steal_with_dma(miso_dma, mosi_dma),
+        unsafe {
+            SubGhz {
+                spi: Spi3::steal_with_dma(miso_dma, mosi_dma),
+            }
         }
     }
 }
@@ -902,7 +904,7 @@ where
     /// # let mut sg = unsafe { stm32wlxx_hal::subghz::SubGhz::steal() };
     /// # let mut delay = new_delay(cp.SYST, &dp.RCC);
     /// use stm32wlxx_hal::{
-    ///     subghz::{wakeup, SleepCfg, StandbyClk},
+    ///     subghz::{SleepCfg, StandbyClk, wakeup},
     ///     util::new_delay,
     /// };
     ///
diff --git a/hal/src/subghz/packet_status.rs b/hal/src/subghz/packet_status.rs
index d9b1fdd5fc1..a71f134de7d 100644
--- a/hal/src/subghz/packet_status.rs
+++ b/hal/src/subghz/packet_status.rs
@@ -88,7 +88,7 @@ impl FskPacketStatus {
     /// # Example
     ///
     /// ```
-    /// use stm32wlxx_hal::{subghz::FskPacketStatus, Ratio};
+    /// use stm32wlxx_hal::{Ratio, subghz::FskPacketStatus};
     ///
     /// let example_data_from_radio: [u8; 4] = [0, 0, 80, 0];
     /// let pkt_status: FskPacketStatus = FskPacketStatus::from(example_data_from_radio);
@@ -105,7 +105,7 @@ impl FskPacketStatus {
     /// # Example
     ///
     /// ```
-    /// use stm32wlxx_hal::{subghz::FskPacketStatus, Ratio};
+    /// use stm32wlxx_hal::{Ratio, subghz::FskPacketStatus};
     ///
     /// let example_data_from_radio: [u8; 4] = [0, 0, 0, 100];
     /// let pkt_status: FskPacketStatus = FskPacketStatus::from(example_data_from_radio);
@@ -208,7 +208,7 @@ impl LoRaPacketStatus {
     /// # Example
     ///
     /// ```
-    /// use stm32wlxx_hal::{subghz::LoRaPacketStatus, Ratio};
+    /// use stm32wlxx_hal::{Ratio, subghz::LoRaPacketStatus};
     ///
     /// let example_data_from_radio: [u8; 4] = [0, 80, 0, 0];
     /// let pkt_status: LoRaPacketStatus = LoRaPacketStatus::from(example_data_from_radio);
@@ -225,7 +225,7 @@ impl LoRaPacketStatus {
     /// # Example
     ///
     /// ```
-    /// use stm32wlxx_hal::{subghz::LoRaPacketStatus, Ratio};
+    /// use stm32wlxx_hal::{Ratio, subghz::LoRaPacketStatus};
     ///
     /// let example_data_from_radio: [u8; 4] = [0, 0, 40, 0];
     /// let pkt_status: LoRaPacketStatus = LoRaPacketStatus::from(example_data_from_radio);
@@ -242,7 +242,7 @@ impl LoRaPacketStatus {
     /// # Example
     ///
     /// ```
-    /// use stm32wlxx_hal::{subghz::LoRaPacketStatus, Ratio};
+    /// use stm32wlxx_hal::{Ratio, subghz::LoRaPacketStatus};
     ///
     /// let example_data_from_radio: [u8; 4] = [0, 0, 0, 80];
     /// let pkt_status: LoRaPacketStatus = LoRaPacketStatus::from(example_data_from_radio);
diff --git a/hal/src/subghz/timeout.rs b/hal/src/subghz/timeout.rs
index c7942afc24f..79ad2b0faae 100644
--- a/hal/src/subghz/timeout.rs
+++ b/hal/src/subghz/timeout.rs
@@ -3,11 +3,7 @@ use core::time::Duration;
 use super::ValueError;
 
 const fn abs_diff(a: u64, b: u64) -> u64 {
-    if a > b {
-        a - b
-    } else {
-        b - a
-    }
+    if a > b { a - b } else { b - a }
 }
 
 /// Timeout argument.
@@ -147,7 +143,7 @@ impl Timeout {
         let nanos: u128 = duration.as_nanos();
         const UPPER_LIMIT: u128 =
             Timeout::MAX.as_nanos() as u128 + (Timeout::RESOLUTION_NANOS as u128) / 2;
-        const LOWER_LIMIT: u128 = ((Timeout::RESOLUTION_NANOS as u128) + 1) / 2;
+        const LOWER_LIMIT: u128 = (Timeout::RESOLUTION_NANOS as u128).div_ceil(2);
 
         if nanos > UPPER_LIMIT {
             Err(ValueError::too_high(nanos, UPPER_LIMIT))
diff --git a/hal/src/uart.rs b/hal/src/uart.rs
index 190d53d9cda..9f9bf7b5fc6 100644
--- a/hal/src/uart.rs
+++ b/hal/src/uart.rs
@@ -1,8 +1,9 @@
 //! Universal synchronous/asynchronous receiver transmitter
 use crate::{
+    Ratio,
     dma::{self, DmaCh},
     gpio::{self},
-    pac, rcc, Ratio,
+    pac, rcc,
 };
 use cortex_m::interrupt::CriticalSection;
 use embedded_hal::prelude::*;
@@ -381,10 +382,12 @@ macro_rules! impl_free_steal {
             ///
             /// [`new`]: Self::new
             pub unsafe fn steal() -> $uart<NoRx, NoTx> {
-                $uart {
-                    uart: pac::Peripherals::steal().$periph,
-                    rx: NoRx::new(),
-                    tx: NoTx::new(),
+                unsafe {
+                    $uart {
+                        uart: pac::Peripherals::steal().$periph,
+                        rx: NoRx::new(),
+                        tx: NoTx::new(),
+                    }
                 }
             }
         }
@@ -429,7 +432,7 @@ macro_rules! impl_tx_en_dis {
             /// ```no_run
             /// use stm32wlxx_hal::{
             ///     cortex_m,
-            ///     gpio::{pins, PortB},
+            ///     gpio::{PortB, pins},
             ///     pac,
             ///     uart::{self, LpUart, NoRx},
             /// };
@@ -470,7 +473,7 @@ macro_rules! impl_tx_en_dis {
             /// use stm32wlxx_hal::{
             ///     cortex_m,
             ///     dma::{AllDma, Dma2Ch7},
-            ///     gpio::{pins, PortB},
+            ///     gpio::{PortB, pins},
             ///     pac,
             ///     uart::{self, LpUart, NoRx},
             /// };
@@ -519,7 +522,7 @@ macro_rules! impl_tx_en_dis {
             /// ```no_run
             /// use stm32wlxx_hal::{
             ///     cortex_m,
-            ///     gpio::{pins, PortB},
+            ///     gpio::{PortB, pins},
             ///     pac,
             ///     uart::{self, LpUart, NoRx, NoTx},
             /// };
@@ -568,7 +571,7 @@ macro_rules! impl_rx_en_dis {
             /// ```no_run
             /// use stm32wlxx_hal::{
             ///     cortex_m,
-            ///     gpio::{pins, PortB},
+            ///     gpio::{PortB, pins},
             ///     pac,
             ///     uart::{self, LpUart, NoTx},
             /// };
@@ -608,7 +611,7 @@ macro_rules! impl_rx_en_dis {
             /// ```no_run
             /// use stm32wlxx_hal::{
             ///     dma::{AllDma, Dma2Ch2},
-            ///     gpio::{pins, PortB},
+            ///     gpio::{PortB, pins},
             ///     pac,
             ///     uart::{self, LpUart, NoTx},
             /// };
@@ -656,7 +659,7 @@ macro_rules! impl_rx_en_dis {
             ///
             /// ```no_run
             /// use stm32wlxx_hal::{
-            ///     gpio::{pins, PortB},
+            ///     gpio::{PortB, pins},
             ///     pac,
             ///     uart::{self, LpUart, NoRx, NoTx},
             /// };
diff --git a/lora-e5-bsp/Cargo.toml b/lora-e5-bsp/Cargo.toml
index 6dd1da22d2c..384dffb3caa 100644
--- a/lora-e5-bsp/Cargo.toml
+++ b/lora-e5-bsp/Cargo.toml
@@ -2,15 +2,15 @@
 name = "lora-e5-bsp"
 description = "Board support package for the seeed LoRa-E5 development kit"
 readme = "README.md"
-
-version = "0.6.1"
-authors = ["Alex Martens <alex@thinglab.org>"]
-edition = "2021"
-rust-version = "1.62"
-license = "MIT OR Apache-2.0"
 keywords = ["arm", "cortex-m", "stm32", "bsp", "seeed"]
 categories = ["embedded", "hardware-support", "no-std"]
-repository = "https://github.com/stm32-rs/stm32wlxx-hal"
+
+authors.workspace = true
+edition.workspace = true
+license.workspace = true
+repository.workspace = true
+rust-version.workspace = true
+version.workspace = true
 
 [features]
 chrono = ["stm32wlxx-hal/chrono"]
diff --git a/lora-e5-bsp/src/led.rs b/lora-e5-bsp/src/led.rs
index 070c34572cb..d6298281100 100644
--- a/lora-e5-bsp/src/led.rs
+++ b/lora-e5-bsp/src/led.rs
@@ -6,7 +6,7 @@ use core::ops::Not;
 use hal::{
     cortex_m::interrupt::CriticalSection,
     embedded_hal::digital::v2::OutputPin,
-    gpio::{self, pins, Output, OutputArgs},
+    gpio::{self, Output, OutputArgs, pins},
 };
 
 const LED_ARGS: OutputArgs = OutputArgs {
@@ -90,7 +90,7 @@ impl D5 {
     /// ```
     pub unsafe fn steal() -> Self {
         Self {
-            gpio: Output::steal(),
+            gpio: unsafe { Output::steal() },
         }
     }
 
diff --git a/lora-e5-bsp/src/lib.rs b/lora-e5-bsp/src/lib.rs
index da156eb0e93..c7e8ab3e7e3 100644
--- a/lora-e5-bsp/src/lib.rs
+++ b/lora-e5-bsp/src/lib.rs
@@ -10,7 +10,7 @@ pub use stm32wlxx_hal as hal;
 
 use hal::{
     cortex_m::interrupt::CriticalSection,
-    gpio::{self, pins, Output, OutputArgs, PinState},
+    gpio::{self, Output, OutputArgs, PinState, pins},
 };
 
 /// RF switch
@@ -28,8 +28,8 @@ impl RfSwitch {
     ///
     /// ```no_run
     /// use lora_e5_bsp::{
-    ///     hal::{cortex_m, gpio::PortA, pac},
     ///     RfSwitch,
+    ///     hal::{cortex_m, gpio::PortA, pac},
     /// };
     ///
     /// let mut dp: pac::Peripherals = pac::Peripherals::take().unwrap();
@@ -63,12 +63,12 @@ impl RfSwitch {
     ///
     /// ```no_run
     /// use lora_e5_bsp::{
+    ///     RfSwitch,
     ///     hal::{
     ///         cortex_m,
-    ///         gpio::{pins, Output, PortA},
+    ///         gpio::{Output, PortA, pins},
     ///         pac,
     ///     },
-    ///     RfSwitch,
     /// };
     ///
     /// let mut dp: pac::Peripherals = pac::Peripherals::take().unwrap();
@@ -87,8 +87,8 @@ impl RfSwitch {
     #[inline]
     pub unsafe fn steal() -> Self {
         RfSwitch {
-            a4: Output::steal(),
-            a5: Output::steal(),
+            a4: unsafe { Output::steal() },
+            a5: unsafe { Output::steal() },
         }
     }
 
@@ -98,8 +98,8 @@ impl RfSwitch {
     ///
     /// ```no_run
     /// use lora_e5_bsp::{
-    ///     hal::{cortex_m, gpio::PortA, pac},
     ///     RfSwitch,
+    ///     hal::{cortex_m, gpio::PortA, pac},
     /// };
     ///
     /// let mut dp: pac::Peripherals = pac::Peripherals::take().unwrap();
@@ -120,8 +120,8 @@ impl RfSwitch {
     ///
     /// ```no_run
     /// use lora_e5_bsp::{
-    ///     hal::{cortex_m, gpio::PortA, pac},
     ///     RfSwitch,
+    ///     hal::{cortex_m, gpio::PortA, pac},
     /// };
     ///
     /// let mut dp: pac::Peripherals = pac::Peripherals::take().unwrap();
diff --git a/lora-e5-bsp/src/pb.rs b/lora-e5-bsp/src/pb.rs
index 57867330f4e..94f2688497c 100644
--- a/lora-e5-bsp/src/pb.rs
+++ b/lora-e5-bsp/src/pb.rs
@@ -2,7 +2,7 @@
 
 use stm32wlxx_hal::{
     cortex_m::interrupt::CriticalSection,
-    gpio::{pins, Exti, Input, PinState, Pull},
+    gpio::{Exti, Input, PinState, Pull, pins},
 };
 
 const PULL: Pull = Pull::Up;
@@ -38,7 +38,7 @@ pub trait PushButton {
     ///         gpio::{Exti, ExtiTrg, PortA},
     ///         pac,
     ///     },
-    ///     pb::{PushButton, D0},
+    ///     pb::{D0, PushButton},
     /// };
     ///
     /// let mut dp: pac::Peripherals = pac::Peripherals::take().unwrap();
@@ -80,7 +80,7 @@ impl D0 {
     /// ```no_run
     /// use lora_e5_bsp::{
     ///     hal::{cortex_m, gpio::PortA, pac},
-    ///     pb::{PushButton, D0},
+    ///     pb::{D0, PushButton},
     /// };
     ///
     /// let mut dp: pac::Peripherals = pac::Peripherals::take().unwrap();
@@ -101,7 +101,7 @@ impl D0 {
     /// ```no_run
     /// use lora_e5_bsp::{
     ///     hal::{cortex_m, gpio::PortA, pac},
-    ///     pb::{PushButton, D0},
+    ///     pb::{D0, PushButton},
     /// };
     ///
     /// let mut dp: pac::Peripherals = pac::Peripherals::take().unwrap();
@@ -136,7 +136,7 @@ impl D0 {
     /// ```
     pub unsafe fn steal() -> Self {
         Self {
-            gpio: Input::steal(),
+            gpio: unsafe { Input::steal() },
         }
     }
 }
@@ -207,7 +207,7 @@ impl Boot {
     /// ```
     pub unsafe fn steal() -> Self {
         Self {
-            gpio: Input::steal(),
+            gpio: unsafe { Input::steal() },
         }
     }
 }
diff --git a/nucleo-wl55jc-bsp/Cargo.toml b/nucleo-wl55jc-bsp/Cargo.toml
index 6ad898ee4c7..7a9e5238675 100644
--- a/nucleo-wl55jc-bsp/Cargo.toml
+++ b/nucleo-wl55jc-bsp/Cargo.toml
@@ -2,15 +2,15 @@
 name = "nucleo-wl55jc-bsp"
 description = "Board support package for the NUCLEO-WL55JC"
 readme = "README.md"
-
-version = "0.6.1"
-authors = ["Alex Martens <alex@thinglab.org>"]
-edition = "2021"
-rust-version = "1.62"
-license = "MIT OR Apache-2.0"
 keywords = ["arm", "cortex-m", "stm32", "bsp", "nucleo"]
 categories = ["embedded", "hardware-support", "no-std"]
-repository = "https://github.com/stm32-rs/stm32wlxx-hal"
+
+authors.workspace = true
+edition.workspace = true
+license.workspace = true
+repository.workspace = true
+rust-version.workspace = true
+version.workspace = true
 
 [features]
 chrono = ["stm32wlxx-hal/chrono"]
diff --git a/nucleo-wl55jc-bsp/src/led.rs b/nucleo-wl55jc-bsp/src/led.rs
index 63b6d82b647..cdc6ecc1c90 100644
--- a/nucleo-wl55jc-bsp/src/led.rs
+++ b/nucleo-wl55jc-bsp/src/led.rs
@@ -5,7 +5,7 @@ use stm32wlxx_hal as hal;
 use hal::{
     cortex_m::interrupt::CriticalSection,
     embedded_hal::digital::v2::{OutputPin, ToggleableOutputPin},
-    gpio::{self, pins, Output, OutputArgs},
+    gpio::{self, Output, OutputArgs, pins},
 };
 
 const LED_ARGS: OutputArgs = OutputArgs {
@@ -116,7 +116,7 @@ impl Red {
     /// ```
     pub unsafe fn steal() -> Self {
         Self {
-            gpio: Output::steal(),
+            gpio: unsafe { Output::steal() },
         }
     }
 }
@@ -203,7 +203,7 @@ impl Green {
     /// ```
     pub unsafe fn steal() -> Self {
         Self {
-            gpio: Output::steal(),
+            gpio: unsafe { Output::steal() },
         }
     }
 }
@@ -290,7 +290,7 @@ impl Blue {
     /// ```
     pub unsafe fn steal() -> Self {
         Self {
-            gpio: Output::steal(),
+            gpio: unsafe { Output::steal() },
         }
     }
 }
diff --git a/nucleo-wl55jc-bsp/src/lib.rs b/nucleo-wl55jc-bsp/src/lib.rs
index 4619eef9aa3..be5511bd5c4 100644
--- a/nucleo-wl55jc-bsp/src/lib.rs
+++ b/nucleo-wl55jc-bsp/src/lib.rs
@@ -10,7 +10,7 @@ pub use stm32wlxx_hal as hal;
 
 use hal::{
     cortex_m::interrupt::CriticalSection,
-    gpio::{self, pins, Output, OutputArgs, PinState},
+    gpio::{self, Output, OutputArgs, PinState, pins},
 };
 
 /// RF switch.
@@ -29,8 +29,8 @@ impl RfSwitch {
     ///
     /// ```no_run
     /// use nucleo_wl55jc_bsp::{
-    ///     hal::{cortex_m, gpio::PortC, pac},
     ///     RfSwitch,
+    ///     hal::{cortex_m, gpio::PortC, pac},
     /// };
     ///
     /// let mut dp: pac::Peripherals = pac::Peripherals::take().unwrap();
@@ -66,12 +66,12 @@ impl RfSwitch {
     ///
     /// ```no_run
     /// use nucleo_wl55jc_bsp::{
+    ///     RfSwitch,
     ///     hal::{
     ///         cortex_m,
-    ///         gpio::{pins, Output, PortC},
+    ///         gpio::{Output, PortC, pins},
     ///         pac,
     ///     },
-    ///     RfSwitch,
     /// };
     ///
     /// let mut dp: pac::Peripherals = pac::Peripherals::take().unwrap();
@@ -91,9 +91,9 @@ impl RfSwitch {
     #[inline]
     pub unsafe fn steal() -> Self {
         RfSwitch {
-            fe_ctrl1: Output::steal(),
-            fe_ctrl2: Output::steal(),
-            fe_ctrl3: Output::steal(),
+            fe_ctrl1: unsafe { Output::steal() },
+            fe_ctrl2: unsafe { Output::steal() },
+            fe_ctrl3: unsafe { Output::steal() },
         }
     }
 
@@ -103,8 +103,8 @@ impl RfSwitch {
     ///
     /// ```no_run
     /// use nucleo_wl55jc_bsp::{
-    ///     hal::{cortex_m, gpio::PortC, pac},
     ///     RfSwitch,
+    ///     hal::{cortex_m, gpio::PortC, pac},
     /// };
     ///
     /// let mut dp: pac::Peripherals = pac::Peripherals::take().unwrap();
@@ -127,8 +127,8 @@ impl RfSwitch {
     ///
     /// ```no_run
     /// use nucleo_wl55jc_bsp::{
-    ///     hal::{cortex_m, gpio::PortC, pac},
     ///     RfSwitch,
+    ///     hal::{cortex_m, gpio::PortC, pac},
     /// };
     ///
     /// let mut dp: pac::Peripherals = pac::Peripherals::take().unwrap();
@@ -151,8 +151,8 @@ impl RfSwitch {
     ///
     /// ```no_run
     /// use nucleo_wl55jc_bsp::{
-    ///     hal::{cortex_m, gpio::PortC, pac},
     ///     RfSwitch,
+    ///     hal::{cortex_m, gpio::PortC, pac},
     /// };
     ///
     /// let mut dp: pac::Peripherals = pac::Peripherals::take().unwrap();
diff --git a/nucleo-wl55jc-bsp/src/pb.rs b/nucleo-wl55jc-bsp/src/pb.rs
index 5652cb358b2..da720b3fcf1 100644
--- a/nucleo-wl55jc-bsp/src/pb.rs
+++ b/nucleo-wl55jc-bsp/src/pb.rs
@@ -1,7 +1,7 @@
 //! Push-buttons
 use stm32wlxx_hal::{
     cortex_m::interrupt::CriticalSection,
-    gpio::{pins, Exti, Input, PinState, Pull},
+    gpio::{Exti, Input, PinState, Pull, pins},
 };
 
 const PULL: Pull = Pull::Up;
@@ -151,7 +151,7 @@ impl Pb3 {
     /// ```
     pub unsafe fn steal() -> Self {
         Self {
-            gpio: Input::steal(),
+            gpio: unsafe { Input::steal() },
         }
     }
 }
@@ -222,7 +222,7 @@ impl Pb2 {
     /// ```
     pub unsafe fn steal() -> Self {
         Self {
-            gpio: Input::steal(),
+            gpio: unsafe { Input::steal() },
         }
     }
 }
@@ -293,7 +293,7 @@ impl Pb1 {
     /// ```
     pub unsafe fn steal() -> Self {
         Self {
-            gpio: Input::steal(),
+            gpio: unsafe { Input::steal() },
         }
     }
 }
diff --git a/testsuite/Cargo.toml b/testsuite/Cargo.toml
index f5ad9707ce8..8c7e3b4558a 100644
--- a/testsuite/Cargo.toml
+++ b/testsuite/Cargo.toml
@@ -1,13 +1,13 @@
 [package]
-authors = [
-    "Alex Martens <alex@thinglab.org>",
-    "Jorge I. <jorge@jorgeig.com>"
-]
 name = "testsuite"
 publish = false
-edition = "2021"
-version = "0.1.0"
-license = "MIT OR Apache-2.0"
+
+authors.workspace = true
+edition.workspace = true
+license.workspace = true
+repository.workspace = true
+rust-version.workspace = true
+version.workspace = true
 
 [[bin]]
 name = "adc"
diff --git a/testsuite/src/adc.rs b/testsuite/src/adc.rs
index 79f15420c5d..d0d4c33de63 100644
--- a/testsuite/src/adc.rs
+++ b/testsuite/src/adc.rs
@@ -1,7 +1,7 @@
 #![no_std]
 #![no_main]
 
-use core::sync::atomic::{compiler_fence, Ordering::SeqCst};
+use core::sync::atomic::{Ordering::SeqCst, compiler_fence};
 use defmt::unwrap;
 use defmt_rtt as _; // global logger
 use nucleo_wl55jc_bsp::hal::{
diff --git a/testsuite/src/aes.rs b/testsuite/src/aes.rs
index b4eafc2da59..054499050d9 100644
--- a/testsuite/src/aes.rs
+++ b/testsuite/src/aes.rs
@@ -1732,9 +1732,11 @@ mod tests {
             let start: u32 = DWT::cycle_count();
             let cipher = aes_gcm::Aes128Gcm::new(key.as_ref().into());
             let nonce = Nonce::from_slice(iv.as_ref().into());
-            let result_tag = unwrap!(cipher
-                .encrypt_in_place_detached(nonce, &gcm.aad, &mut buf[..gcm.pt.len()])
-                .ok());
+            let result_tag = unwrap!(
+                cipher
+                    .encrypt_in_place_detached(nonce, &gcm.aad, &mut buf[..gcm.pt.len()])
+                    .ok()
+            );
             total_elapsed += DWT::cycle_count().wrapping_sub(start);
 
             let result_tag: [u8; 16] = unwrap!(result_tag.try_into());
@@ -2098,7 +2100,10 @@ mod tests {
                 &ZERO_16B,
                 &IV,
                 ASSOCIATED_DATA,
-                unsafe { &mut BUF },
+                #[allow(static_mut_refs)]
+                unsafe {
+                    &mut BUF
+                },
                 &mut encrypt_tag
             ))
         });
@@ -2108,7 +2113,7 @@ mod tests {
             encrypt_elapsed
         );
 
-        assert_ne!(unsafe { &BUF }, PLAINTEXT);
+        assert_ne!(&raw const BUF, PLAINTEXT);
         defmt::assert_ne!(encrypt_tag, ZERO_16B);
 
         let mut decrypt_tag: [u32; 4] = [0; 4];
@@ -2117,12 +2122,15 @@ mod tests {
                 &ZERO_16B,
                 &IV,
                 ASSOCIATED_DATA,
-                unsafe { &mut BUF },
+                #[allow(static_mut_refs)]
+                unsafe {
+                    &mut BUF
+                },
                 &mut decrypt_tag
             ))
         });
 
-        assert_eq!(unsafe { &BUF }, PLAINTEXT);
+        assert_eq!(&raw const BUF, PLAINTEXT);
         defmt::assert_eq!(decrypt_tag, encrypt_tag);
 
         defmt::info!(
diff --git a/testsuite/src/flash.rs b/testsuite/src/flash.rs
index 7f864476a48..b6b27828956 100644
--- a/testsuite/src/flash.rs
+++ b/testsuite/src/flash.rs
@@ -6,10 +6,10 @@ use defmt::unwrap;
 use defmt_rtt as _; // global logger
 use nucleo_wl55jc_bsp::hal::{
     cortex_m,
-    flash::{self, flash_range, AlignedAddr, Error, Flash, Page},
+    flash::{self, AlignedAddr, Error, Flash, Page, flash_range},
     pac::{self, DWT},
     rcc,
-    rng::{self, rand_core::RngCore, Rng},
+    rng::{self, Rng, rand_core::RngCore},
 };
 use panic_probe as _;
 use rand::Rng as RngTrait;
@@ -131,6 +131,7 @@ mod tests {
     #[test]
     fn fast_program(ta: &mut TestArgs) {
         static mut BUF: [u64; 32] = [0; 32];
+        #[allow(static_mut_refs)]
         unsafe {
             BUF.iter_mut()
                 .for_each(|word| *word = ta.rng.gen_range(1..u64::MAX - 1))
@@ -138,6 +139,7 @@ mod tests {
 
         let mut flash: Flash = Flash::unlock(&mut ta.flash);
 
+        #[allow(static_mut_refs)]
         let elapsed: u32 =
             stopwatch(|| unwrap!(unsafe { flash.fast_program(BUF.as_ptr(), ta.addr as *mut u64) }));
 
diff --git a/testsuite/src/i2c.rs b/testsuite/src/i2c.rs
index 87466ed1837..7d489baf5ab 100644
--- a/testsuite/src/i2c.rs
+++ b/testsuite/src/i2c.rs
@@ -6,7 +6,7 @@ use defmt_rtt as _; // global logger
 use nucleo_wl55jc_bsp::hal::{
     cortex_m,
     embedded_hal::blocking::i2c::WriteRead,
-    gpio::{pins, PortA, PortB},
+    gpio::{PortA, PortB, pins},
     i2c::{I2c1, I2c2},
     pac::{self, interrupt},
     rcc,
@@ -79,7 +79,9 @@ mod tests {
 
     #[test]
     fn sht31_measurement(i2c: &mut I2c1<(pins::B8, pins::B7)>) {
-        defmt::warn!("A SHT31 sensor must be connected to the board on pins B8 (SCL) & B7 (SDA) for this test to work");
+        defmt::warn!(
+            "A SHT31 sensor must be connected to the board on pins B8 (SCL) & B7 (SDA) for this test to work"
+        );
         let cmd: [u8; 2] = [0x2C, 0x06];
         let mut response: [u8; 6] = [0; 6];
 
@@ -92,7 +94,9 @@ mod tests {
 
     #[test]
     fn loopback(i2c: &mut I2c1<(pins::B8, pins::B7)>) {
-        defmt::warn!("I2C1 pins B8 (SCL) and B7 (SDA) must be connected to I2C pins A12 (SCL) and A11 (SDA) for this test to pass");
+        defmt::warn!(
+            "I2C1 pins B8 (SCL) and B7 (SDA) must be connected to I2C pins A12 (SCL) and A11 (SDA) for this test to pass"
+        );
 
         let cmd: [u8; 1] = [LOOPBACK_DATA_IN];
         let mut response: [u8; 1] = [0; 1];
diff --git a/testsuite/src/lptim.rs b/testsuite/src/lptim.rs
index 1974199031a..ed227f8c3ac 100644
--- a/testsuite/src/lptim.rs
+++ b/testsuite/src/lptim.rs
@@ -7,7 +7,7 @@ use nucleo_wl55jc_bsp::hal::{
     cortex_m,
     embedded_hal::digital::v2::ToggleableOutputPin,
     embedded_hal::timer::CountDown,
-    gpio::{pins, Output, PortA, PortB},
+    gpio::{Output, PortA, PortB, pins},
     lptim::{self, Filter, LpTim, LpTim1, LpTim2, LpTim3, Prescaler, TrgPol},
     pac::{self, DWT},
     rcc,
diff --git a/testsuite/src/pka.rs b/testsuite/src/pka.rs
index f6c35c9a721..363838d0afd 100644
--- a/testsuite/src/pka.rs
+++ b/testsuite/src/pka.rs
@@ -7,7 +7,7 @@ use nucleo_wl55jc_bsp::hal::{
     cortex_m,
     pac::{self, DWT},
     pka::{
-        curve::NIST_P256, EcdsaPublicKey, EcdsaSignError, EcdsaSignature, EcdsaVerifyError, Pka,
+        EcdsaPublicKey, EcdsaSignError, EcdsaSignature, EcdsaVerifyError, Pka, curve::NIST_P256,
     },
     rcc,
 };
@@ -140,7 +140,7 @@ mod tests {
         // rust-crypto p256 for comparison
         {
             use ecdsa::hazmat::SignPrimitive;
-            use p256::{elliptic_curve::ops::Reduce, Scalar};
+            use p256::{Scalar, elliptic_curve::ops::Reduce};
 
             let hash_bytes: [u8; 32] = into_bytes(HASH_SWAP);
             let private_key_bytes: [u8; 32] = into_bytes(PRIVATE_KEY_SWAP);
@@ -154,9 +154,11 @@ mod tests {
             let ephemeral_scalar: Scalar = Scalar::reduce_bytes(&ephemeral_secret.to_bytes());
 
             let start: u32 = DWT::cycle_count();
-            let (signature, _) = unwrap!(static_scalar
-                .try_sign_prehashed(ephemeral_scalar, &prehashed_message_as_scalar.to_bytes())
-                .ok());
+            let (signature, _) = unwrap!(
+                static_scalar
+                    .try_sign_prehashed(ephemeral_scalar, &prehashed_message_as_scalar.to_bytes())
+                    .ok()
+            );
             let elapsed: u32 = DWT::cycle_count().wrapping_sub(start);
             defmt::info!("Approximate cycles per rust-crypto p256 sign: {}", elapsed);
 
@@ -218,8 +220,8 @@ mod tests {
 
         // rust-crypto p256 for comparison
         {
-            use ecdsa::{hazmat::VerifyPrimitive, Signature};
-            use p256::{elliptic_curve::ops::Reduce, PublicKey, Scalar};
+            use ecdsa::{Signature, hazmat::VerifyPrimitive};
+            use p256::{PublicKey, Scalar, elliptic_curve::ops::Reduce};
 
             let hash_bytes: [u8; 32] = into_bytes(HASH_SWAP);
 
@@ -232,10 +234,9 @@ mod tests {
 
             let prehashed_message_as_scalar: Scalar = Scalar::reduce_bytes((&hash_bytes).into());
 
-            let signature: Signature<_> =
-                unwrap!(
-                    Signature::from_scalars(into_bytes(R_SIGN_SWAP), into_bytes(S_SIGN_SWAP)).ok()
-                );
+            let signature: Signature<_> = unwrap!(
+                Signature::from_scalars(into_bytes(R_SIGN_SWAP), into_bytes(S_SIGN_SWAP)).ok()
+            );
 
             let start: u32 = DWT::cycle_count();
             let result = public_key
diff --git a/testsuite/src/rcc.rs b/testsuite/src/rcc.rs
index 0eb74cc7db8..f7fcdab9777 100644
--- a/testsuite/src/rcc.rs
+++ b/testsuite/src/rcc.rs
@@ -9,8 +9,8 @@ use itertools::iproduct;
 use nucleo_wl55jc_bsp::hal::{
     cortex_m::{self, interrupt::CriticalSection},
     pac,
-    pwr::{enter_lprun_msi, exit_lprun, LprunRange},
-    rcc::{self, lsi_hz, set_sysclk_msi_max, setup_lsi, LsiPre, MsiRange, Vos},
+    pwr::{LprunRange, enter_lprun_msi, exit_lprun},
+    rcc::{self, LsiPre, MsiRange, Vos, lsi_hz, set_sysclk_msi_max, setup_lsi},
 };
 use panic_probe as _;
 
@@ -29,10 +29,12 @@ impl SysClkSrc {
         rcc: &mut pac::RCC,
         cs: &CriticalSection,
     ) {
-        match self {
-            SysClkSrc::Msi(range) => rcc::set_sysclk_msi(flash, pwr, rcc, *range, cs),
-            SysClkSrc::Hse(vos) => rcc::set_sysclk_hse(flash, pwr, rcc, *vos, cs),
-            SysClkSrc::Hsi => rcc::set_sysclk_hsi(flash, pwr, rcc, cs),
+        unsafe {
+            match self {
+                SysClkSrc::Msi(range) => rcc::set_sysclk_msi(flash, pwr, rcc, *range, cs),
+                SysClkSrc::Hse(vos) => rcc::set_sysclk_hse(flash, pwr, rcc, *vos, cs),
+                SysClkSrc::Hsi => rcc::set_sysclk_hsi(flash, pwr, rcc, cs),
+            }
         }
     }
 
diff --git a/testsuite/src/rng.rs b/testsuite/src/rng.rs
index c01f96a9549..f60d7ce2dd9 100644
--- a/testsuite/src/rng.rs
+++ b/testsuite/src/rng.rs
@@ -5,7 +5,7 @@ use defmt::unwrap;
 use defmt_rtt as _; // global logger
 use nucleo_wl55jc_bsp::hal::{
     cortex_m, pac, rcc,
-    rng::{rand_core::RngCore, Clk, Rng},
+    rng::{Clk, Rng, rand_core::RngCore},
 };
 use panic_probe as _;
 
@@ -47,7 +47,7 @@ mod tests {
     #[test]
     fn cha_cha(rng: &mut Rng) {
         defmt::warn!("Test results are only valid for release mode");
-        use rand_chacha::{rand_core::SeedableRng, ChaCha12Rng, ChaCha20Rng, ChaCha8Rng};
+        use rand_chacha::{ChaCha8Rng, ChaCha12Rng, ChaCha20Rng, rand_core::SeedableRng};
 
         let mut seed: [u8; 32] = [0; 32];
 
@@ -67,24 +67,28 @@ mod tests {
         static mut BUF: [u8; BUF_SIZE] = [0; BUF_SIZE];
 
         let start: u32 = pac::DWT::cycle_count();
+        #[allow(static_mut_refs)]
         let ret = cha20.try_fill_bytes(unsafe { &mut BUF });
         let end: u32 = pac::DWT::cycle_count();
         defmt::assert!(ret.is_ok());
         let cha20cyc: u32 = end.wrapping_sub(start);
 
         let start: u32 = pac::DWT::cycle_count();
+        #[allow(static_mut_refs)]
         let ret = cha12.try_fill_bytes(unsafe { &mut BUF });
         let end: u32 = pac::DWT::cycle_count();
         defmt::assert!(ret.is_ok());
         let cha12cyc: u32 = end.wrapping_sub(start);
 
         let start: u32 = pac::DWT::cycle_count();
+        #[allow(static_mut_refs)]
         let ret = cha8.try_fill_bytes(unsafe { &mut BUF });
         let end: u32 = pac::DWT::cycle_count();
         defmt::assert!(ret.is_ok());
         let cha8cyc: u32 = end.wrapping_sub(start);
 
         let start: u32 = pac::DWT::cycle_count();
+        #[allow(static_mut_refs)]
         let ret = rng.try_fill_bytes(unsafe { &mut BUF });
         let end: u32 = pac::DWT::cycle_count();
         defmt::assert!(ret.is_ok());
diff --git a/testsuite/src/rtc.rs b/testsuite/src/rtc.rs
index 8330f668ddc..11996f80e6c 100644
--- a/testsuite/src/rtc.rs
+++ b/testsuite/src/rtc.rs
@@ -7,7 +7,7 @@ use nucleo_wl55jc_bsp::hal::{
     chrono::{Datelike, Duration, NaiveDate, NaiveDateTime, NaiveTime, Timelike},
     cortex_m,
     pac::{self, DWT},
-    rcc::{self, pulse_reset_backup_domain, setup_lsi, LsiPre},
+    rcc::{self, LsiPre, pulse_reset_backup_domain, setup_lsi},
     rtc::{self, Alarm, Rtc},
 };
 use panic_probe as _;
@@ -79,8 +79,8 @@ fn test_set_date_time_with_clk(clk: rtc::Clk) -> Rtc {
     defmt::assert_eq!(rtc_date_time.month(), set_dt.month());
     defmt::assert_eq!(rtc_date_time.day(), set_dt.day());
 
-    let before: i64 = set_dt.timestamp_millis();
-    let after: i64 = rtc_date_time.timestamp_millis();
+    let before: i64 = set_dt.and_utc().timestamp_millis();
+    let after: i64 = rtc_date_time.and_utc().timestamp_millis();
     defmt::debug!(
         "Timestamp before {} after {} Δ {}",
         before,
diff --git a/testsuite/src/spi.rs b/testsuite/src/spi.rs
index b1adff31c88..f68c9d89b24 100644
--- a/testsuite/src/spi.rs
+++ b/testsuite/src/spi.rs
@@ -15,7 +15,7 @@ use nucleo_wl55jc_bsp::hal::{
     pac::{self, DWT},
     rcc,
     spi::{
-        BaudRate, Mode, NoMiso, NoMosi, NoSck, Phase, Polarity, Spi, MODE_0, MODE_1, MODE_2, MODE_3,
+        BaudRate, MODE_0, MODE_1, MODE_2, MODE_3, Mode, NoMiso, NoMosi, NoSck, Phase, Polarity, Spi,
     },
 };
 use panic_probe as _;
@@ -105,7 +105,7 @@ impl SpiSlave {
 }
 
 unsafe fn setup() -> TestArgs {
-    let mut dp: pac::Peripherals = pac::Peripherals::steal();
+    let mut dp: pac::Peripherals = unsafe { pac::Peripherals::steal() };
     let dma: AllDma = AllDma::split(dp.DMAMUX, dp.DMA1, dp.DMA2, &mut dp.RCC);
     let pa: PortA = PortA::split(dp.GPIOA, &mut dp.RCC);
     let _: PortC = PortC::split(dp.GPIOC, &mut dp.RCC);
diff --git a/testsuite/src/subghz.rs b/testsuite/src/subghz.rs
index b155f20bde8..43cd5a68afb 100644
--- a/testsuite/src/subghz.rs
+++ b/testsuite/src/subghz.rs
@@ -9,6 +9,7 @@ use nucleo_wl55jc_bsp as bsp;
 use static_assertions as sa;
 
 use bsp::{
+    RfSwitch,
     hal::{
         cortex_m::{self, delay::Delay},
         dma::{AllDma, Dma1Ch1, Dma2Ch1},
@@ -18,16 +19,15 @@ use bsp::{
         rng::{self, Rng},
         spi::{SgMiso, SgMosi},
         subghz::{
-            rfbusys, wakeup, AddrComp, CalibrateImage, CfgIrq, CmdStatus, CodingRate, CrcType,
-            FallbackMode, FskBandwidth, FskBitrate, FskFdev, FskModParams, FskPulseShape,
-            GenericPacketParams, HeaderType, Irq, LoRaBandwidth, LoRaModParams, LoRaPacketParams,
-            LoRaSyncWord, Ocp, PaConfig, PacketType, PktCtrl, PreambleDetection, RampTime, RegMode,
-            RfFreq, SleepCfg, SpreadingFactor, StandbyClk, Startup, Status, StatusMode, SubGhz,
-            TcxoMode, TcxoTrim, Timeout, TxParams,
+            AddrComp, CalibrateImage, CfgIrq, CmdStatus, CodingRate, CrcType, FallbackMode,
+            FskBandwidth, FskBitrate, FskFdev, FskModParams, FskPulseShape, GenericPacketParams,
+            HeaderType, Irq, LoRaBandwidth, LoRaModParams, LoRaPacketParams, LoRaSyncWord, Ocp,
+            PaConfig, PacketType, PktCtrl, PreambleDetection, RampTime, RegMode, RfFreq, SleepCfg,
+            SpreadingFactor, StandbyClk, Startup, Status, StatusMode, SubGhz, TcxoMode, TcxoTrim,
+            Timeout, TxParams, rfbusys, wakeup,
         },
         util::new_delay,
     },
-    RfSwitch,
 };
 
 type MySubghz = SubGhz<Dma1Ch1, Dma2Ch1>;
@@ -326,9 +326,10 @@ mod tests {
         while rfbusys() {}
         let start: u32 = DWT::cycle_count();
         unwrap!(ta.sg.write_buffer(0, &DATA));
-        unwrap!(ta
-            .sg
-            .read_buffer(0, unsafe { unwrap!(core::ptr::addr_of_mut!(BUF).as_mut()) }));
+        unwrap!(
+            ta.sg
+                .read_buffer(0, unsafe { unwrap!(core::ptr::addr_of_mut!(BUF).as_mut()) })
+        );
         let end: u32 = DWT::cycle_count();
         defmt::info!("Cycles 255B: {}", end - start);
         defmt::assert_eq!(DATA, unsafe { BUF });
diff --git a/testsuite/src/uart.rs b/testsuite/src/uart.rs
index 504c39017e0..6acd6a22cac 100644
--- a/testsuite/src/uart.rs
+++ b/testsuite/src/uart.rs
@@ -8,7 +8,7 @@ use nucleo_wl55jc_bsp::hal::{
     cortex_m,
     dma::{AllDma, Dma1Ch3, Dma2Ch6},
     embedded_hal::prelude::*,
-    gpio::{pins, PortA, PortC},
+    gpio::{PortA, PortC, pins},
     pac, rcc,
     uart::{self, LpUart, Uart1},
 };