|
79 | 79 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\ |
80 | 80 | STM32F479xx */ |
81 | 81 |
|
82 | | -#ifndef VECT_TAB_OFFSET |
83 | | -#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. |
84 | | - This value must be a multiple of 0x200. */ |
85 | | -#else |
86 | | -#define USER_VECT_TAB_ADDRESS |
87 | | -#endif |
88 | | - |
89 | 82 | /* Note: Following vector table addresses must be defined in line with linker |
90 | 83 | configuration. */ |
91 | | -/*!< Uncomment the following line if you need to relocate the vector table |
92 | | - anywhere in Flash or Sram, else the vector table is kept at the automatic |
93 | | - remap of boot address selected */ |
94 | | -/* #define USER_VECT_TAB_ADDRESS */ |
95 | 84 |
|
96 | | -#if defined(USER_VECT_TAB_ADDRESS) |
| 85 | +/*!< Uncomment the following line and change the address |
| 86 | + if you need to relocate your vector Table at a custom base address (+ VECT_TAB_OFFSET) */ |
| 87 | +/* #define VECT_TAB_BASE_ADDRESS 0x08000000 */ |
| 88 | + |
97 | 89 | /*!< Uncomment the following line if you need to relocate your vector Table |
98 | | - in Sram else user remap will be done in Flash. */ |
| 90 | + in Sram else user remap will be done by default in Flash. */ |
99 | 91 | /* #define VECT_TAB_SRAM */ |
| 92 | + |
| 93 | +#ifndef VECT_TAB_OFFSET |
| 94 | +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. |
| 95 | + This value must be a multiple of 0x200. */ |
| 96 | +#endif |
| 97 | + |
| 98 | +#ifndef VECT_TAB_BASE_ADDRESS |
100 | 99 | #if defined(VECT_TAB_SRAM) |
101 | 100 | #define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field. |
102 | 101 | This value must be a multiple of 0x200. */ |
103 | 102 | #else |
104 | 103 | #define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. |
105 | 104 | This value must be a multiple of 0x200. */ |
106 | 105 | #endif /* VECT_TAB_SRAM */ |
107 | | -#endif /* USER_VECT_TAB_ADDRESS */ |
| 106 | +#endif /* VECT_TAB_BASE_ADDRESS */ |
| 107 | + |
| 108 | + |
108 | 109 | /******************************************************************************/ |
109 | 110 |
|
110 | 111 | /** |
@@ -171,28 +172,29 @@ void SystemInit(void) |
171 | 172 | RCC->CR |= (uint32_t)0x00000001; |
172 | 173 |
|
173 | 174 | /* Reset CFGR register */ |
174 | | - RCC->CFGR = 0x00000000; |
| 175 | + RCC->CFGR = (uint32_t)0x00000000; |
175 | 176 |
|
176 | 177 | /* Reset HSEON, CSSON and PLLON bits */ |
177 | 178 | RCC->CR &= (uint32_t)0xFEF6FFFF; |
178 | 179 |
|
179 | 180 | /* Reset PLLCFGR register */ |
180 | | - RCC->PLLCFGR = 0x24003010; |
| 181 | + RCC->PLLCFGR = (uint32_t)0x24003010; |
181 | 182 |
|
182 | 183 | /* Reset HSEBYP bit */ |
183 | 184 | RCC->CR &= (uint32_t)0xFFFBFFFF; |
184 | 185 |
|
185 | | - /* Disable all interrupts */ |
186 | | - RCC->CIR = 0x00000000; |
| 186 | +#if defined(RCC_CIR_PLLSAIRDYC) |
| 187 | + RCC->CIR = (uint32_t)0x00FF0000; |
| 188 | +#else |
| 189 | + RCC->CIR = (uint32_t)0x00BF0000; |
| 190 | +#endif |
187 | 191 |
|
188 | 192 | #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) |
189 | 193 | SystemInit_ExtMemCtl(); |
190 | 194 | #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ |
191 | 195 |
|
192 | 196 | /* Configure the Vector Table location -------------------------------------*/ |
193 | | -#if defined(USER_VECT_TAB_ADDRESS) |
194 | | - SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ |
195 | | -#endif /* USER_VECT_TAB_ADDRESS */ |
| 197 | + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; |
196 | 198 | } |
197 | 199 |
|
198 | 200 | /** |
|
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