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Remove use of TimerMap_CONFIG (part 1)
Timer clock source. Signed-off-by: Frederic.Pillon <[email protected]>
1 parent 2d65501 commit 13af5f0

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11 files changed

+181
-105
lines changed

11 files changed

+181
-105
lines changed

cores/arduino/stm32/pinmap.c

Lines changed: 0 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -92,12 +92,3 @@ uint32_t timermap_irq(TIM_TypeDef *tim, const TimerMap* map) {
9292
}
9393
return (uint32_t)0;
9494
}
95-
96-
uint32_t timermap_clkSrc(TIM_TypeDef *tim, const TimerMap* map) {
97-
while (map->timer != NULL) {
98-
if (map->timer == tim)
99-
return map->clk_src;
100-
map++;
101-
}
102-
return (uint32_t)0;
103-
}

cores/arduino/stm32/pinmap.h

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -36,7 +36,6 @@ typedef struct {
3636
typedef struct {
3737
TIM_TypeDef *timer;
3838
IRQn_Type irq;
39-
uint8_t clk_src;
4039
} TimerMap;
4140

4241
bool pin_in_pinmap(PinName pin, const PinMap* map);
@@ -49,7 +48,6 @@ uint32_t pinmap_find_function(PinName pin, const PinMap* map);
4948
uint32_t pinmap_merge(uint32_t a, uint32_t b);
5049

5150
uint32_t timermap_irq(TIM_TypeDef *tim, const TimerMap* map);
52-
uint32_t timermap_clkSrc(TIM_TypeDef *tim, const TimerMap* map);
5351

5452
#ifdef __cplusplus
5553
}

cores/arduino/stm32/timer.c

Lines changed: 88 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -421,7 +421,93 @@ void TimerHandleDeinit(stimer_t *obj)
421421
*/
422422
uint8_t getTimerClkSrc(TIM_TypeDef* tim)
423423
{
424-
return (uint8_t)timermap_clkSrc(tim, TimerMap_CONFIG);
424+
uint8_t clkSrc = 0;
425+
426+
if(tim != (TimerMap *)NC)
427+
#ifdef STM32F0xx
428+
/* TIMx source CLK is PCKL1 */
429+
clkSrc = 1;
430+
#else
431+
{
432+
/* Get source clock depending on TIM instance */
433+
switch ((uint32_t)tim) {
434+
#if defined(TIM2_BASE)
435+
case (uint32_t)TIM2:
436+
#endif
437+
#if defined(TIM3_BASE)
438+
case (uint32_t)TIM3:
439+
#endif
440+
#if defined(TIM4_BASE)
441+
case (uint32_t)TIM4:
442+
#endif
443+
#if defined(TIM5_BASE)
444+
case (uint32_t)TIM5:
445+
#endif
446+
#if defined(TIM6_BASE)
447+
case (uint32_t)TIM6:
448+
#endif
449+
#if defined(TIM7_BASE)
450+
case (uint32_t)TIM7:
451+
#endif
452+
#if defined(TIM12_BASE)
453+
case (uint32_t)TIM12:
454+
#endif
455+
#if defined(TIM13_BASE)
456+
case (uint32_t)TIM13:
457+
#endif
458+
#if defined(TIM14_BASE)
459+
case (uint32_t)TIM14:
460+
#endif
461+
#if defined(TIM18_BASE)
462+
case (uint32_t)TIM18:
463+
#endif
464+
clkSrc = 1;
465+
break;
466+
#if defined(TIM1_BASE)
467+
case (uint32_t)TIM1:
468+
#endif
469+
#if defined(TIM8_BASE)
470+
case (uint32_t)TIM8:
471+
#endif
472+
#if defined(TIM9_BASE)
473+
case (uint32_t)TIM9:
474+
#endif
475+
#if defined(TIM10_BASE)
476+
case (uint32_t)TIM10:
477+
#endif
478+
#if defined(TIM11_BASE)
479+
case (uint32_t)TIM11:
480+
#endif
481+
#if defined(TIM15_BASE)
482+
case (uint32_t)TIM15:
483+
#endif
484+
#if defined(TIM16_BASE)
485+
case (uint32_t)TIM16:
486+
#endif
487+
#if defined(TIM17_BASE)
488+
case (uint32_t)TIM17:
489+
#endif
490+
#if defined(TIM19_BASE)
491+
case (uint32_t)TIM19:
492+
#endif
493+
#if defined(TIM20_BASE)
494+
case (uint32_t)TIM20:
495+
#endif
496+
#if defined(TIM21_BASE)
497+
case (uint32_t)TIM21:
498+
#endif
499+
#if defined(TIM22_BASE)
500+
case (uint32_t)TIM22:
501+
#endif
502+
clkSrc = 2;
503+
break;
504+
default:
505+
printf("TIM: Unknown timer instance");
506+
break;
507+
}
508+
}
509+
#endif
510+
return clkSrc;
425511
}
426512

427513
/**
@@ -450,6 +536,7 @@ uint32_t getTimerClkFreq(TIM_TypeDef* tim)
450536
#endif
451537
default:
452538
case 0:
539+
printf("TIM: Unknown clock source");
453540
break;
454541
}
455542
/* When TIMPRE bit of the RCC_DCKCFGR register is reset,

variants/DISCO_F407VG/PeripheralPins.c

Lines changed: 15 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -295,19 +295,19 @@ const PinMap PinMap_CAN_TD[] = {
295295
};
296296

297297
const TimerMap TimerMap_CONFIG[] = {
298-
{TIM1, TIM1_UP_TIM10_IRQn, 2},
299-
{TIM2, TIM2_IRQn, 1},
300-
{TIM3, TIM3_IRQn, 1},
301-
{TIM4, TIM4_IRQn, 1},
302-
{TIM5, TIM5_IRQn, 1},
303-
{TIM6, TIM6_DAC_IRQn, 1},
304-
{TIM7, TIM7_IRQn, 1},
305-
{TIM8, TIM8_UP_TIM13_IRQn, 2},
306-
{TIM9, TIM1_BRK_TIM9_IRQn, 2},
307-
{TIM10, TIM1_UP_TIM10_IRQn, 2},
308-
{TIM11, TIM1_TRG_COM_TIM11_IRQn, 2},
309-
{TIM12, TIM8_BRK_TIM12_IRQn, 1},
310-
{TIM13, TIM8_UP_TIM13_IRQn, 1},
311-
{TIM14, TIM8_TRG_COM_TIM14_IRQn, 1},
312-
{NULL, 0, 0}
298+
{TIM1, TIM1_UP_TIM10_IRQn},
299+
{TIM2, TIM2_IRQn},
300+
{TIM3, TIM3_IRQn},
301+
{TIM4, TIM4_IRQn},
302+
{TIM5, TIM5_IRQn},
303+
{TIM6, TIM6_DAC_IRQn},
304+
{TIM7, TIM7_IRQn},
305+
{TIM8, TIM8_UP_TIM13_IRQn},
306+
{TIM9, TIM1_BRK_TIM9_IRQn},
307+
{TIM10, TIM1_UP_TIM10_IRQn},
308+
{TIM11, TIM1_TRG_COM_TIM11_IRQn},
309+
{TIM12, TIM8_BRK_TIM12_IRQn},
310+
{TIM13, TIM8_UP_TIM13_IRQn},
311+
{TIM14, TIM8_TRG_COM_TIM14_IRQn},
312+
{NULL, 0}
313313
};

variants/DISCO_F746NG/PeripheralPins.c

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -386,19 +386,19 @@ const PinMap PinMap_CAN_TD[] = {
386386
};
387387

388388
const TimerMap TimerMap_CONFIG[] = {
389-
{TIM1, TIM1_UP_TIM10_IRQn, 2},
390-
{TIM2, TIM2_IRQn, 1},
391-
{TIM3, TIM3_IRQn, 1},
392-
{TIM4, TIM4_IRQn, 1},
393-
{TIM5, TIM5_IRQn, 1},
394-
{TIM6, TIM6_DAC_IRQn, 1},
395-
{TIM7, TIM7_IRQn, 1},
396-
{TIM8, TIM8_UP_TIM13_IRQn, 2},
397-
{TIM9, TIM1_BRK_TIM9_IRQn, 2},
398-
{TIM10, TIM1_UP_TIM10_IRQn, 2},
399-
{TIM11, TIM1_TRG_COM_TIM11_IRQn, 2},
400-
{TIM12, TIM8_BRK_TIM12_IRQn, 1},
401-
{TIM13, TIM8_UP_TIM13_IRQn, 1},
402-
{TIM14, TIM8_TRG_COM_TIM14_IRQn, 1},
403-
{NULL, 0, 0}
404-
};
389+
{TIM1, TIM1_UP_TIM10_IRQn},
390+
{TIM2, TIM2_IRQn},
391+
{TIM3, TIM3_IRQn},
392+
{TIM4, TIM4_IRQn},
393+
{TIM5, TIM5_IRQn},
394+
{TIM6, TIM6_DAC_IRQn},
395+
{TIM7, TIM7_IRQn},
396+
{TIM8, TIM8_UP_TIM13_IRQn},
397+
{TIM9, TIM1_BRK_TIM9_IRQn},
398+
{TIM10, TIM1_UP_TIM10_IRQn},
399+
{TIM11, TIM1_TRG_COM_TIM11_IRQn},
400+
{TIM12, TIM8_BRK_TIM12_IRQn},
401+
{TIM13, TIM8_UP_TIM13_IRQn},
402+
{TIM14, TIM8_TRG_COM_TIM14_IRQn},
403+
{NULL, 0}
404+
};

variants/NUCLEO_F030R8/PeripheralPins.c

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -181,12 +181,12 @@ const PinMap PinMap_SPI_SSEL[] = {
181181
// No CAN
182182

183183
const TimerMap TimerMap_CONFIG[] = {
184-
{TIM1, TIM1_BRK_UP_TRG_COM_IRQn, 1},
185-
{TIM3, TIM3_IRQn, 1},
186-
{TIM6, TIM6_DAC_IRQn, 1},
187-
{TIM14, TIM14_IRQn, 1},
188-
{TIM15, TIM15_IRQn, 1},
189-
{TIM16, TIM16_IRQn, 1},
190-
{TIM17, TIM17_IRQn, 1},
191-
{NULL, 0, 0}
184+
{TIM1, TIM1_BRK_UP_TRG_COM_IRQn},
185+
{TIM3, TIM3_IRQn},
186+
{TIM6, TIM6_DAC_IRQn},
187+
{TIM14, TIM14_IRQn},
188+
{TIM15, TIM15_IRQn},
189+
{TIM16, TIM16_IRQn},
190+
{TIM17, TIM17_IRQn},
191+
{NULL, 0}
192192
};

variants/NUCLEO_F091RC/PeripheralPins.c

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -252,14 +252,14 @@ const PinMap PinMap_CAN_TD[] = {
252252
};
253253

254254
const TimerMap TimerMap_CONFIG[] = {
255-
{TIM1, TIM1_BRK_UP_TRG_COM_IRQn, 1},
256-
{TIM2, TIM2_IRQn, 1},
257-
{TIM3, TIM3_IRQn, 1},
258-
{TIM6, TIM6_DAC_IRQn, 1},
259-
{TIM7, TIM7_IRQn, 1},
260-
{TIM14, TIM14_IRQn, 1},
261-
{TIM15, TIM15_IRQn, 1},
262-
{TIM16, TIM16_IRQn, 1},
263-
{TIM17, TIM17_IRQn, 1},
264-
{NULL, 0, 0}
255+
{TIM1, TIM1_BRK_UP_TRG_COM_IRQn},
256+
{TIM2, TIM2_IRQn},
257+
{TIM3, TIM3_IRQn},
258+
{TIM6, TIM6_DAC_IRQn},
259+
{TIM7, TIM7_IRQn},
260+
{TIM14, TIM14_IRQn},
261+
{TIM15, TIM15_IRQn},
262+
{TIM16, TIM16_IRQn},
263+
{TIM17, TIM17_IRQn},
264+
{NULL, 0}
265265
};

variants/NUCLEO_F303RE/PeripheralPins.c

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -292,16 +292,16 @@ const PinMap PinMap_CAN_TD[] = {
292292
};
293293

294294
const TimerMap TimerMap_CONFIG[] = {
295-
{TIM1, TIM1_UP_TIM16_IRQn, 2},
296-
{TIM2, TIM2_IRQn, 1},
297-
{TIM3, TIM3_IRQn, 1},
298-
{TIM4, TIM4_IRQn, 1},
299-
{TIM6, TIM6_DAC_IRQn, 1},
300-
{TIM7, TIM7_IRQn, 1},
301-
{TIM8, TIM8_UP_IRQn, 2},
302-
{TIM15, TIM1_BRK_TIM15_IRQn, 2},
303-
{TIM16, TIM1_UP_TIM16_IRQn, 2},
304-
{TIM17, TIM1_TRG_COM_TIM17_IRQn, 2},
305-
{TIM20, TIM20_UP_IRQn, 2},
306-
{NULL, 0, 0}
295+
{TIM1, TIM1_UP_TIM16_IRQn},
296+
{TIM2, TIM2_IRQn},
297+
{TIM3, TIM3_IRQn},
298+
{TIM4, TIM4_IRQn},
299+
{TIM6, TIM6_DAC_IRQn},
300+
{TIM7, TIM7_IRQn},
301+
{TIM8, TIM8_UP_IRQn},
302+
{TIM15, TIM1_BRK_TIM15_IRQn},
303+
{TIM16, TIM1_UP_TIM16_IRQn},
304+
{TIM17, TIM1_TRG_COM_TIM17_IRQn},
305+
{TIM20, TIM20_UP_IRQn},
306+
{NULL, 0}
307307
};

variants/NUCLEO_F429ZI/PeripheralPins.c

Lines changed: 15 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -339,19 +339,19 @@ const PinMap PinMap_CAN_TD[] = {
339339
};
340340

341341
const TimerMap TimerMap_CONFIG[] = {
342-
{TIM1, TIM1_UP_TIM10_IRQn, 2},
343-
{TIM2, TIM2_IRQn, 1},
344-
{TIM3, TIM3_IRQn, 1},
345-
{TIM4, TIM4_IRQn, 1},
346-
{TIM5, TIM5_IRQn, 1},
347-
{TIM6, TIM6_DAC_IRQn, 1},
348-
{TIM7, TIM7_IRQn, 1},
349-
{TIM8, TIM8_UP_TIM13_IRQn, 2},
350-
{TIM9, TIM1_BRK_TIM9_IRQn, 2},
351-
{TIM10, TIM1_UP_TIM10_IRQn, 2},
352-
{TIM11, TIM1_TRG_COM_TIM11_IRQn, 2},
353-
{TIM12, TIM8_BRK_TIM12_IRQn, 1},
354-
{TIM13, TIM8_UP_TIM13_IRQn, 1},
355-
{TIM14, TIM8_TRG_COM_TIM14_IRQn, 1},
356-
{NULL, 0, 0}
342+
{TIM1, TIM1_UP_TIM10_IRQn},
343+
{TIM2, TIM2_IRQn},
344+
{TIM3, TIM3_IRQn},
345+
{TIM4, TIM4_IRQn},
346+
{TIM5, TIM5_IRQn},
347+
{TIM6, TIM6_DAC_IRQn},
348+
{TIM7, TIM7_IRQn},
349+
{TIM8, TIM8_UP_TIM13_IRQn},
350+
{TIM9, TIM1_BRK_TIM9_IRQn},
351+
{TIM10, TIM1_UP_TIM10_IRQn},
352+
{TIM11, TIM1_TRG_COM_TIM11_IRQn},
353+
{TIM12, TIM8_BRK_TIM12_IRQn},
354+
{TIM13, TIM8_UP_TIM13_IRQn},
355+
{TIM14, TIM8_TRG_COM_TIM14_IRQn},
356+
{NULL, 0}
357357
};

variants/NUCLEO_L053R8/PeripheralPins.c

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -197,9 +197,9 @@ const PinMap PinMap_CAN_TD[] = {
197197
};
198198

199199
const TimerMap TimerMap_CONFIG[] = {
200-
{TIM2, TIM2_IRQn, 1},
201-
{TIM6, TIM6_DAC_IRQn, 1},
202-
{TIM21, TIM21_IRQn, 2},
203-
{TIM22, TIM22_IRQn, 2},
204-
{NULL, 0, 0}
200+
{TIM2, TIM2_IRQn},
201+
{TIM6, TIM6_DAC_IRQn},
202+
{TIM21, TIM21_IRQn},
203+
{TIM22, TIM22_IRQn},
204+
{NULL, 0}
205205
};

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