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fpistmfpistm
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fix(wb0): HAL and LL warnings
Signed-off-by: Frederic Pillon <[email protected]>
1 parent c5d860e commit 2697593

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5 files changed

+47
-4
lines changed

5 files changed

+47
-4
lines changed

‎system/Drivers/STM32WB0x_HAL_Driver/Inc/stm32wb0x_ll_dma.h

Lines changed: 40 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -430,6 +430,7 @@ typedef struct
430430
*/
431431
__STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
432432
{
433+
(void)DMAx;
433434
SET_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_EN);
434435
}
435436

@@ -450,6 +451,7 @@ __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
450451
*/
451452
__STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
452453
{
454+
(void)DMAx;
453455
CLEAR_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_EN);
454456
}
455457

@@ -470,6 +472,7 @@ __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
470472
*/
471473
__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
472474
{
475+
(void)DMAx;
473476
return ((READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
474477
DMA_CCR_EN) == (DMA_CCR_EN)) ? 1UL : 0UL);
475478
}
@@ -506,6 +509,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Cha
506509
*/
507510
__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
508511
{
512+
(void)DMAx;
509513
MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
510514
DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL,
511515
Configuration);
@@ -533,6 +537,7 @@ __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel,
533537
*/
534538
__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
535539
{
540+
(void)DMAx;
536541
MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
537542
DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction);
538543
}
@@ -558,6 +563,7 @@ __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t
558563
*/
559564
__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
560565
{
566+
(void)DMAx;
561567
return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
562568
DMA_CCR_DIR | DMA_CCR_MEM2MEM));
563569
}
@@ -584,6 +590,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint
584590
*/
585591
__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
586592
{
593+
(void)DMAx;
587594
MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_CIRC,
588595
Mode);
589596
}
@@ -607,6 +614,7 @@ __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_
607614
*/
608615
__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
609616
{
617+
(void)DMAx;
610618
return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
611619
DMA_CCR_CIRC));
612620
}
@@ -631,6 +639,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
631639
*/
632640
__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
633641
{
642+
(void)DMAx;
634643
MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_PINC,
635644
PeriphOrM2MSrcIncMode);
636645
}
@@ -654,6 +663,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel
654663
*/
655664
__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
656665
{
666+
(void)DMAx;
657667
return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
658668
DMA_CCR_PINC));
659669
}
@@ -678,6 +688,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Cha
678688
*/
679689
__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
680690
{
691+
(void)DMAx;
681692
MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_MINC,
682693
MemoryOrM2MDstIncMode);
683694
}
@@ -701,6 +712,7 @@ __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel
701712
*/
702713
__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
703714
{
715+
(void)DMAx;
704716
return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
705717
DMA_CCR_MINC));
706718
}
@@ -726,6 +738,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Cha
726738
*/
727739
__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
728740
{
741+
(void)DMAx;
729742
MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_PSIZE,
730743
PeriphOrM2MSrcDataSize);
731744
}
@@ -750,6 +763,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, u
750763
*/
751764
__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)
752765
{
766+
(void)DMAx;
753767
return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
754768
DMA_CCR_PSIZE));
755769
}
@@ -775,6 +789,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channe
775789
*/
776790
__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
777791
{
792+
(void)DMAx;
778793
MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_MSIZE,
779794
MemoryOrM2MDstDataSize);
780795
}
@@ -799,6 +814,7 @@ __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, u
799814
*/
800815
__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)
801816
{
817+
(void)DMAx;
802818
return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
803819
DMA_CCR_MSIZE));
804820
}
@@ -825,6 +841,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channe
825841
*/
826842
__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
827843
{
844+
(void)DMAx;
828845
MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_PL,
829846
Priority);
830847
}
@@ -850,6 +867,7 @@ __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t
850867
*/
851868
__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
852869
{
870+
(void)DMAx;
853871
return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
854872
DMA_CCR_PL));
855873
}
@@ -874,6 +892,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint3
874892
*/
875893
__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
876894
{
895+
(void)DMAx;
877896
MODIFY_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CNDTR,
878897
DMA_CNDTR_NDT, NbData);
879898
}
@@ -897,6 +916,7 @@ __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, u
897916
*/
898917
__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
899918
{
919+
(void)DMAx;
900920
return (READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CNDTR,
901921
DMA_CNDTR_NDT));
902922
}
@@ -928,6 +948,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channe
928948
__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
929949
uint32_t DstAddress, uint32_t Direction)
930950
{
951+
(void)DMAx;
931952
/* Direction Memory to Periph */
932953
if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
933954
{
@@ -962,6 +983,7 @@ __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel,
962983
*/
963984
__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
964985
{
986+
(void)DMAx;
965987
WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR, MemoryAddress);
966988
}
967989

@@ -985,6 +1007,7 @@ __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel
9851007
*/
9861008
__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
9871009
{
1010+
(void)DMAx;
9881011
WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR, PeriphAddress);
9891012
}
9901013

@@ -1006,6 +1029,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel
10061029
*/
10071030
__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
10081031
{
1032+
(void)DMAx;
10091033
return (READ_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR));
10101034
}
10111035

@@ -1027,6 +1051,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Cha
10271051
*/
10281052
__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
10291053
{
1054+
(void)DMAx;
10301055
return (READ_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR));
10311056
}
10321057

@@ -1050,6 +1075,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Cha
10501075
*/
10511076
__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
10521077
{
1078+
(void)DMAx;
10531079
WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR, MemoryAddress);
10541080
}
10551081

@@ -1073,6 +1099,7 @@ __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel
10731099
*/
10741100
__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
10751101
{
1102+
(void)DMAx;
10761103
WRITE_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR, MemoryAddress);
10771104
}
10781105

@@ -1094,6 +1121,7 @@ __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel
10941121
*/
10951122
__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
10961123
{
1124+
(void)DMAx;
10971125
return (READ_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CPAR));
10981126
}
10991127

@@ -1115,6 +1143,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Cha
11151143
*/
11161144
__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
11171145
{
1146+
(void)DMAx;
11181147
return (READ_REG(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CMAR));
11191148
}
11201149

@@ -1137,6 +1166,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Cha
11371166
*/
11381167
__STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request)
11391168
{
1169+
(void)DMAx;
11401170
MODIFY_REG(__LL_DMA_INSTANCE_TO_DMAMUX_CCR(DMAx, Channel - 1U)->CxCR, DMAMUX_CxCR_DMAREQ_ID, Request);
11411171
}
11421172

@@ -1158,6 +1188,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel
11581188
*/
11591189
__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel)
11601190
{
1191+
(void)DMAx;
11611192
return (READ_BIT(__LL_DMA_INSTANCE_TO_DMAMUX_CCR(DMAx, Channel - 1U)->CxCR, DMAMUX_CxCR_DMAREQ_ID));
11621193
}
11631194

@@ -1897,6 +1928,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE8(DMA_TypeDef *DMAx)
18971928
*/
18981929
__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
18991930
{
1931+
(void)DMAx;
19001932
SET_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TCIE);
19011933
}
19021934

@@ -1917,6 +1949,7 @@ __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
19171949
*/
19181950
__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
19191951
{
1952+
(void)DMAx;
19201953
SET_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_HTIE);
19211954
}
19221955

@@ -1937,6 +1970,7 @@ __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
19371970
*/
19381971
__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
19391972
{
1973+
(void)DMAx;
19401974
SET_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TEIE);
19411975
}
19421976

@@ -1957,6 +1991,7 @@ __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
19571991
*/
19581992
__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
19591993
{
1994+
(void)DMAx;
19601995
CLEAR_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TCIE);
19611996
}
19621997

@@ -1977,6 +2012,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
19772012
*/
19782013
__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
19792014
{
2015+
(void)DMAx;
19802016
CLEAR_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_HTIE);
19812017
}
19822018

@@ -1997,6 +2033,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
19972033
*/
19982034
__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
19992035
{
2036+
(void)DMAx;
20002037
CLEAR_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR, DMA_CCR_TEIE);
20012038
}
20022039

@@ -2017,6 +2054,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
20172054
*/
20182055
__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
20192056
{
2057+
(void)DMAx;
20202058
return ((READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
20212059
DMA_CCR_TCIE) == (DMA_CCR_TCIE)) ? 1UL : 0UL);
20222060
}
@@ -2038,6 +2076,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Chann
20382076
*/
20392077
__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
20402078
{
2079+
(void)DMAx;
20412080
return ((READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
20422081
DMA_CCR_HTIE) == (DMA_CCR_HTIE)) ? 1UL : 0UL);
20432082
}
@@ -2059,6 +2098,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Chann
20592098
*/
20602099
__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
20612100
{
2101+
(void)DMAx;
20622102
return ((READ_BIT(__LL_DMA_INSTANCE_TO_CHANNEL(DMAx, Channel - 1U)->CCR,
20632103
DMA_CCR_TEIE) == (DMA_CCR_TEIE)) ? 1UL : 0UL);
20642104
}

‎system/Drivers/STM32WB0x_HAL_Driver/Inc/stm32wb0x_ll_radio_timer.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -445,6 +445,8 @@ __STATIC_INLINE uint32_t LL_RADIO_TIMER_IsEnabledCPUWakeupTimerForceSleeping(WAK
445445
__STATIC_INLINE void LL_RADIO_TIMER_SetSleepRequestMode(WAKEUP_TypeDef *WAKEUPx, uint8_t mode)
446446
{
447447
#if defined(STM32WB09)
448+
(void)WAKEUPx; // No operation for STM32WB09
449+
(void)mode; // No operation for STM32WB09
448450
return;
449451
#else
450452
MODIFY_REG_FIELD(WAKEUP->BLUE_SLEEP_REQUEST_MODE, WAKEUP_BLUE_SLEEP_REQUEST_MODE_SLEEP_REQ_MODE, (mode & 0x7));
@@ -460,6 +462,7 @@ __STATIC_INLINE void LL_RADIO_TIMER_SetSleepRequestMode(WAKEUP_TypeDef *WAKEUPx,
460462
__STATIC_INLINE uint32_t LL_RADIO_TIMER_GetSleepRequestMode(WAKEUP_TypeDef *WAKEUPx)
461463
{
462464
#if defined(STM32WB09)
465+
(void)WAKEUPx; // No operation for STM32WB09
463466
return 0;
464467
#else
465468
return (uint32_t)(READ_REG(WAKEUP->BLUE_SLEEP_REQUEST_MODE) & WAKEUP_BLUE_SLEEP_REQUEST_MODE_SLEEP_REQ_MODE);

‎system/Drivers/STM32WB0x_HAL_Driver/Src/stm32wb0x_hal_flash_ex.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -109,7 +109,7 @@ static void FLASH_KeyWrite(void);
109109
*/
110110
HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
111111
{
112-
HAL_StatusTypeDef status;
112+
HAL_StatusTypeDef status = HAL_ERROR;
113113
uint32_t index;
114114

115115
/* Check the parameters */

‎system/Drivers/STM32WB0x_HAL_Driver/Src/stm32wb0x_hal_radio_timer.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1129,7 +1129,7 @@ static void _get_calibration_data(CalibrationDataTypeDef *calibrationData)
11291129
int32_t a2;
11301130

11311131
period = LL_RADIO_TIMER_GetLSIPeriod(RADIO_CTRL);
1132-
while (period != LL_RADIO_TIMER_GetLSIPeriod(RADIO_CTRL) || period == 0)
1132+
while (period != (int32_t)LL_RADIO_TIMER_GetLSIPeriod(RADIO_CTRL) || period == 0)
11331133
{
11341134
period = LL_RADIO_TIMER_GetLSIPeriod(RADIO_CTRL);
11351135
}
@@ -1143,7 +1143,7 @@ static void _get_calibration_data(CalibrationDataTypeDef *calibrationData)
11431143
mult = 0x753 ;
11441144
freq = LL_RADIO_TIMER_GetLSIFrequency(RADIO_CTRL);
11451145

1146-
while (freq != LL_RADIO_TIMER_GetLSIFrequency(RADIO_CTRL) || freq == 0)
1146+
while (freq != (int32_t)LL_RADIO_TIMER_GetLSIFrequency(RADIO_CTRL) || freq == 0)
11471147
{
11481148
freq = LL_RADIO_TIMER_GetLSIFrequency(RADIO_CTRL);
11491149
}

‎system/Drivers/STM32WB0x_HAL_Driver/Src/stm32wb0x_ll_adc.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -24,7 +24,7 @@
2424
#ifdef USE_FULL_ASSERT
2525
#include "stm32_assert.h"
2626
#else
27-
#define assert_param(expr) ((void)0UL)
27+
#define assert_param(expr) ((void)0U)
2828
#endif /* USE_FULL_ASSERT */
2929

3030
/** @addtogroup STM32WB0x_LL_Driver

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