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[L4] Update STM32L4xx CMSIS to v1.5.1
Included in STM32CubeL4 FW V1.14.0 Note: Trailing spaces have been cleaned. Signed-off-by: Frederic.Pillon <[email protected]>
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‎system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l412xx.h

Lines changed: 28 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -12,29 +12,13 @@
1212
******************************************************************************
1313
* @attention
1414
*
15-
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
15+
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
16+
* All rights reserved.</center></h2>
1617
*
17-
* Redistribution and use in source and binary forms, with or without modification,
18-
* are permitted provided that the following conditions are met:
19-
* 1. Redistributions of source code must retain the above copyright notice,
20-
* this list of conditions and the following disclaimer.
21-
* 2. Redistributions in binary form must reproduce the above copyright notice,
22-
* this list of conditions and the following disclaimer in the documentation
23-
* and/or other materials provided with the distribution.
24-
* 3. Neither the name of STMicroelectronics nor the names of its contributors
25-
* may be used to endorse or promote products derived from this software
26-
* without specific prior written permission.
27-
*
28-
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
29-
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30-
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
31-
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
32-
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33-
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
34-
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
35-
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
36-
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37-
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
18+
* This software component is licensed by ST under BSD 3-Clause license,
19+
* the "License"; You may not use this file except in compliance with the
20+
* License. You may obtain a copy of the License at:
21+
* opensource.org/licenses/BSD-3-Clause
3822
*
3923
******************************************************************************
4024
*/
@@ -93,7 +77,7 @@ typedef enum
9377
SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
9478
/****** STM32 specific Interrupt Numbers **********************************************************************/
9579
WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
96-
PVD_PVM_IRQn = 1, /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts */
80+
PVD_PVM_IRQn = 1, /*!< PVD/PVM1/PVM3/PVM4 through EXTI Line detection Interrupts */
9781
TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
9882
RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
9983
FLASH_IRQn = 4, /*!< FLASH global Interrupt */
@@ -1340,6 +1324,10 @@ typedef struct
13401324
#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */
13411325
#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */
13421326

1327+
#define ADC_SMPR1_SMPPLUS_Pos (31U)
1328+
#define ADC_SMPR1_SMPPLUS_Msk (0x1UL << ADC_SMPR1_SMPPLUS_Pos) /*!< 0x80000000 */
1329+
#define ADC_SMPR1_SMPPLUS ADC_SMPR1_SMPPLUS_Msk /*!< ADC channels sampling time additional setting */
1330+
13431331
/******************** Bit definition for ADC_SMPR2 register *****************/
13441332
#define ADC_SMPR2_SMP10_Pos (0U)
13451333
#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */
@@ -3217,7 +3205,7 @@ typedef struct
32173205
#define FLASH_CR_MER1_Msk (0x1UL << FLASH_CR_MER1_Pos) /*!< 0x00000004 */
32183206
#define FLASH_CR_MER1 FLASH_CR_MER1_Msk
32193207
#define FLASH_CR_PNB_Pos (3U)
3220-
#define FLASH_CR_PNB_Msk (0x7FUL << FLASH_CR_PNB_Pos) /*!< 0x000003F8 */
3208+
#define FLASH_CR_PNB_Msk (0x3FUL << FLASH_CR_PNB_Pos) /*!< 0x000001F8 */
32213209
#define FLASH_CR_PNB FLASH_CR_PNB_Msk
32223210
#define FLASH_CR_STRT_Pos (16U)
32233211
#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
@@ -4821,9 +4809,9 @@ typedef struct
48214809
#define PWR_CR3_EIWUL_Pos (15U)
48224810
#define PWR_CR3_EIWUL_Msk (0x1UL << PWR_CR3_EIWUL_Pos) /*!< 0x00008000 */
48234811
#define PWR_CR3_EIWUL PWR_CR3_EIWUL_Msk /*!< Enable Internal Wake-up line */
4824-
#define PWR_CR3_EN_ULP_Pos (11U)
4825-
#define PWR_CR3_EN_ULP_Msk (0x1UL << PWR_CR3_EN_ULP_Pos) /*!< 0x00000800 */
4826-
#define PWR_CR3_EN_ULP PWR_CR3_EN_ULP_Msk /*!< Enable ULP BORL, BORH and PVD for STOP2 and Standby modes */
4812+
#define PWR_CR3_ENULP_Pos (11U)
4813+
#define PWR_CR3_ENULP_Msk (0x1UL << PWR_CR3_ENULP_Pos) /*!< 0x00000800 */
4814+
#define PWR_CR3_ENULP PWR_CR3_ENULP_Msk /*!< Enable ULP BORL, BORH and PVD for STOP2 and Standby modes */
48274815
#define PWR_CR3_APC_Pos (10U)
48284816
#define PWR_CR3_APC_Msk (0x1UL << PWR_CR3_APC_Pos) /*!< 0x00000400 */
48294817
#define PWR_CR3_APC PWR_CR3_APC_Msk /*!< Apply pull-up and pull-down configuration */
@@ -7321,6 +7309,12 @@ typedef struct
73217309
#define QUADSPI_CR_SSHIFT_Pos (4U)
73227310
#define QUADSPI_CR_SSHIFT_Msk (0x1UL << QUADSPI_CR_SSHIFT_Pos) /*!< 0x00000010 */
73237311
#define QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk /*!< Sample Shift */
7312+
#define QUADSPI_CR_DFM_Pos (6U)
7313+
#define QUADSPI_CR_DFM_Msk (0x1UL << QUADSPI_CR_DFM_Pos) /*!< 0x00000040 */
7314+
#define QUADSPI_CR_DFM QUADSPI_CR_DFM_Msk /*!< Dual-flash mode */
7315+
#define QUADSPI_CR_FSEL_Pos (7U)
7316+
#define QUADSPI_CR_FSEL_Msk (0x1UL << QUADSPI_CR_FSEL_Pos) /*!< 0x00000080 */
7317+
#define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk /*!< Flash memory selection */
73247318
#define QUADSPI_CR_FTHRES_Pos (8U)
73257319
#define QUADSPI_CR_FTHRES_Msk (0xFUL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000F00 */
73267320
#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[3:0] FIFO Level */
@@ -7450,6 +7444,9 @@ typedef struct
74507444
#define QUADSPI_CCR_SIOO_Pos (28U)
74517445
#define QUADSPI_CCR_SIOO_Msk (0x1UL << QUADSPI_CCR_SIOO_Pos) /*!< 0x10000000 */
74527446
#define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk /*!< SIOO: Send Instruction Only Once Mode */
7447+
#define QUADSPI_CCR_DHHC_Pos (30U)
7448+
#define QUADSPI_CCR_DHHC_Msk (0x1UL << QUADSPI_CCR_DHHC_Pos) /*!< 0x40000000 */
7449+
#define QUADSPI_CCR_DHHC QUADSPI_CCR_DHHC_Msk /*!< DHHC: DDR hold */
74537450
#define QUADSPI_CCR_DDRM_Pos (31U)
74547451
#define QUADSPI_CCR_DDRM_Msk (0x1UL << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */
74557452
#define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk /*!< DDRM: Double Data Rate Mode */
@@ -8606,7 +8603,7 @@ typedef struct
86068603

86078604
/******************************************************************************/
86088605
/* */
8609-
/* Low Power Timer (LPTTIM) */
8606+
/* Low Power Timer (LPTIM) */
86108607
/* */
86118608
/******************************************************************************/
86128609
/****************** Bit definition for LPTIM_ISR register *******************/
@@ -10593,6 +10590,9 @@ typedef struct
1059310590
#define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1) || \
1059410591
((INSTANCE) == LPTIM2))
1059510592

10593+
/****************** LPTIM Instances : supporting the encoder mode *************/
10594+
#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
10595+
1059610596
/****************** TIM Instances : All supported instances *******************/
1059710597
#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
1059810598
((INSTANCE) == TIM2) || \

‎system/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l422xx.h

Lines changed: 28 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -12,29 +12,13 @@
1212
******************************************************************************
1313
* @attention
1414
*
15-
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
15+
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
16+
* All rights reserved.</center></h2>
1617
*
17-
* Redistribution and use in source and binary forms, with or without modification,
18-
* are permitted provided that the following conditions are met:
19-
* 1. Redistributions of source code must retain the above copyright notice,
20-
* this list of conditions and the following disclaimer.
21-
* 2. Redistributions in binary form must reproduce the above copyright notice,
22-
* this list of conditions and the following disclaimer in the documentation
23-
* and/or other materials provided with the distribution.
24-
* 3. Neither the name of STMicroelectronics nor the names of its contributors
25-
* may be used to endorse or promote products derived from this software
26-
* without specific prior written permission.
27-
*
28-
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
29-
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30-
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
31-
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
32-
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33-
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
34-
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
35-
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
36-
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37-
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
18+
* This software component is licensed by ST under BSD 3-Clause license,
19+
* the "License"; You may not use this file except in compliance with the
20+
* License. You may obtain a copy of the License at:
21+
* opensource.org/licenses/BSD-3-Clause
3822
*
3923
******************************************************************************
4024
*/
@@ -93,7 +77,7 @@ typedef enum
9377
SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
9478
/****** STM32 specific Interrupt Numbers **********************************************************************/
9579
WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
96-
PVD_PVM_IRQn = 1, /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts */
80+
PVD_PVM_IRQn = 1, /*!< PVD/PVM1/PVM3/PVM4 through EXTI Line detection Interrupts */
9781
TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
9882
RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
9983
FLASH_IRQn = 4, /*!< FLASH global Interrupt */
@@ -1375,6 +1359,10 @@ typedef struct
13751359
#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */
13761360
#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */
13771361

1362+
#define ADC_SMPR1_SMPPLUS_Pos (31U)
1363+
#define ADC_SMPR1_SMPPLUS_Msk (0x1UL << ADC_SMPR1_SMPPLUS_Pos) /*!< 0x80000000 */
1364+
#define ADC_SMPR1_SMPPLUS ADC_SMPR1_SMPPLUS_Msk /*!< ADC channels sampling time additional setting */
1365+
13781366
/******************** Bit definition for ADC_SMPR2 register *****************/
13791367
#define ADC_SMPR2_SMP10_Pos (0U)
13801368
#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */
@@ -3433,7 +3421,7 @@ typedef struct
34333421
#define FLASH_CR_MER1_Msk (0x1UL << FLASH_CR_MER1_Pos) /*!< 0x00000004 */
34343422
#define FLASH_CR_MER1 FLASH_CR_MER1_Msk
34353423
#define FLASH_CR_PNB_Pos (3U)
3436-
#define FLASH_CR_PNB_Msk (0x7FUL << FLASH_CR_PNB_Pos) /*!< 0x000003F8 */
3424+
#define FLASH_CR_PNB_Msk (0x3FUL << FLASH_CR_PNB_Pos) /*!< 0x000001F8 */
34373425
#define FLASH_CR_PNB FLASH_CR_PNB_Msk
34383426
#define FLASH_CR_STRT_Pos (16U)
34393427
#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
@@ -5037,9 +5025,9 @@ typedef struct
50375025
#define PWR_CR3_EIWUL_Pos (15U)
50385026
#define PWR_CR3_EIWUL_Msk (0x1UL << PWR_CR3_EIWUL_Pos) /*!< 0x00008000 */
50395027
#define PWR_CR3_EIWUL PWR_CR3_EIWUL_Msk /*!< Enable Internal Wake-up line */
5040-
#define PWR_CR3_EN_ULP_Pos (11U)
5041-
#define PWR_CR3_EN_ULP_Msk (0x1UL << PWR_CR3_EN_ULP_Pos) /*!< 0x00000800 */
5042-
#define PWR_CR3_EN_ULP PWR_CR3_EN_ULP_Msk /*!< Enable ULP BORL, BORH and PVD for STOP2 and Standby modes */
5028+
#define PWR_CR3_ENULP_Pos (11U)
5029+
#define PWR_CR3_ENULP_Msk (0x1UL << PWR_CR3_ENULP_Pos) /*!< 0x00000800 */
5030+
#define PWR_CR3_ENULP PWR_CR3_ENULP_Msk /*!< Enable ULP BORL, BORH and PVD for STOP2 and Standby modes */
50435031
#define PWR_CR3_APC_Pos (10U)
50445032
#define PWR_CR3_APC_Msk (0x1UL << PWR_CR3_APC_Pos) /*!< 0x00000400 */
50455033
#define PWR_CR3_APC PWR_CR3_APC_Msk /*!< Apply pull-up and pull-down configuration */
@@ -7546,6 +7534,12 @@ typedef struct
75467534
#define QUADSPI_CR_SSHIFT_Pos (4U)
75477535
#define QUADSPI_CR_SSHIFT_Msk (0x1UL << QUADSPI_CR_SSHIFT_Pos) /*!< 0x00000010 */
75487536
#define QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk /*!< Sample Shift */
7537+
#define QUADSPI_CR_DFM_Pos (6U)
7538+
#define QUADSPI_CR_DFM_Msk (0x1UL << QUADSPI_CR_DFM_Pos) /*!< 0x00000040 */
7539+
#define QUADSPI_CR_DFM QUADSPI_CR_DFM_Msk /*!< Dual-flash mode */
7540+
#define QUADSPI_CR_FSEL_Pos (7U)
7541+
#define QUADSPI_CR_FSEL_Msk (0x1UL << QUADSPI_CR_FSEL_Pos) /*!< 0x00000080 */
7542+
#define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk /*!< Flash memory selection */
75497543
#define QUADSPI_CR_FTHRES_Pos (8U)
75507544
#define QUADSPI_CR_FTHRES_Msk (0xFUL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000F00 */
75517545
#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[3:0] FIFO Level */
@@ -7675,6 +7669,9 @@ typedef struct
76757669
#define QUADSPI_CCR_SIOO_Pos (28U)
76767670
#define QUADSPI_CCR_SIOO_Msk (0x1UL << QUADSPI_CCR_SIOO_Pos) /*!< 0x10000000 */
76777671
#define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk /*!< SIOO: Send Instruction Only Once Mode */
7672+
#define QUADSPI_CCR_DHHC_Pos (30U)
7673+
#define QUADSPI_CCR_DHHC_Msk (0x1UL << QUADSPI_CCR_DHHC_Pos) /*!< 0x40000000 */
7674+
#define QUADSPI_CCR_DHHC QUADSPI_CCR_DHHC_Msk /*!< DHHC: DDR hold */
76787675
#define QUADSPI_CCR_DDRM_Pos (31U)
76797676
#define QUADSPI_CCR_DDRM_Msk (0x1UL << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */
76807677
#define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk /*!< DDRM: Double Data Rate Mode */
@@ -8831,7 +8828,7 @@ typedef struct
88318828

88328829
/******************************************************************************/
88338830
/* */
8834-
/* Low Power Timer (LPTTIM) */
8831+
/* Low Power Timer (LPTIM) */
88358832
/* */
88368833
/******************************************************************************/
88378834
/****************** Bit definition for LPTIM_ISR register *******************/
@@ -10821,6 +10818,9 @@ typedef struct
1082110818
#define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1) || \
1082210819
((INSTANCE) == LPTIM2))
1082310820

10821+
/****************** LPTIM Instances : supporting the encoder mode *************/
10822+
#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
10823+
1082410824
/****************** TIM Instances : All supported instances *******************/
1082510825
#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
1082610826
((INSTANCE) == TIM2) || \

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