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Update HAL for STM32F0xx (from STM32CubeF0 V1.8.0)
Signed-off-by: Frederic.Pillon <[email protected]>
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‎system/Drivers/STM32F0xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h

Lines changed: 74 additions & 51 deletions
Original file line numberDiff line numberDiff line change
@@ -2,14 +2,12 @@
22
******************************************************************************
33
* @file stm32_hal_legacy.h
44
* @author MCD Application Team
5-
* @version V1.5.0
6-
* @date 04-November-2016
75
* @brief This file contains aliases definition for the STM32Cube HAL constants
86
* macros and functions maintained for legacy purpose.
97
******************************************************************************
108
* @attention
119
*
12-
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
10+
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
1311
*
1412
* Redistribution and use in source and binary forms, with or without modification,
1513
* are permitted provided that the following conditions are met:
@@ -241,9 +239,9 @@
241239
#define DAC1_CHANNEL_1 DAC_CHANNEL_1
242240
#define DAC1_CHANNEL_2 DAC_CHANNEL_2
243241
#define DAC2_CHANNEL_1 DAC_CHANNEL_1
244-
#define DAC_WAVE_NONE ((uint32_t)0x00000000U)
245-
#define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0)
246-
#define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1)
242+
#define DAC_WAVE_NONE 0x00000000U
243+
#define DAC_WAVE_NOISE DAC_CR_WAVE1_0
244+
#define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1
247245
#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE
248246
#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
249247
#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
@@ -382,7 +380,7 @@
382380
/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
383381
* @{
384382
*/
385-
#if defined(STM32L4) || defined(STM32F7)
383+
#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7)
386384
#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE
387385
#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE
388386
#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8
@@ -917,48 +915,45 @@
917915
#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK
918916
#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK
919917

920-
#define ETH_MMCCR ((uint32_t)0x00000100U)
921-
#define ETH_MMCRIR ((uint32_t)0x00000104U)
922-
#define ETH_MMCTIR ((uint32_t)0x00000108U)
923-
#define ETH_MMCRIMR ((uint32_t)0x0000010CU)
924-
#define ETH_MMCTIMR ((uint32_t)0x00000110U)
925-
#define ETH_MMCTGFSCCR ((uint32_t)0x0000014CU)
926-
#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150U)
927-
#define ETH_MMCTGFCR ((uint32_t)0x00000168U)
928-
#define ETH_MMCRFCECR ((uint32_t)0x00000194U)
929-
#define ETH_MMCRFAECR ((uint32_t)0x00000198U)
930-
#define ETH_MMCRGUFCR ((uint32_t)0x000001C4U)
918+
#define ETH_MMCCR 0x00000100U
919+
#define ETH_MMCRIR 0x00000104U
920+
#define ETH_MMCTIR 0x00000108U
921+
#define ETH_MMCRIMR 0x0000010CU
922+
#define ETH_MMCTIMR 0x00000110U
923+
#define ETH_MMCTGFSCCR 0x0000014CU
924+
#define ETH_MMCTGFMSCCR 0x00000150U
925+
#define ETH_MMCTGFCR 0x00000168U
926+
#define ETH_MMCRFCECR 0x00000194U
927+
#define ETH_MMCRFAECR 0x00000198U
928+
#define ETH_MMCRGUFCR 0x000001C4U
931929

932-
#define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */
933-
#define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */
934-
#define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */
935-
#define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */
936-
#define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
937-
#define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
938-
#define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
939-
#define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */
940-
#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */
941-
#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
942-
#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
943-
#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */
944-
#define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */
945-
#define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */
946-
#define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
947-
#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */
948-
#define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */
949-
#if defined(STM32F1)
950-
#else
951-
#define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000000) /* Rx FIFO read controller IDLE state */
952-
#define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000020) /* Rx FIFO read controller Reading frame data */
953-
#define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000040) /* Rx FIFO read controller Reading frame status (or time-stamp) */
954-
#endif
955-
#define ETH_MAC_READCONTROLLER_FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */
956-
#define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */
957-
#define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */
958-
#define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */
959-
#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */
960-
#define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */
961-
#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */
930+
#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */
931+
#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */
932+
#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */
933+
#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */
934+
#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
935+
#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
936+
#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
937+
#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */
938+
#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */
939+
#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
940+
#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
941+
#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */
942+
#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */
943+
#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */
944+
#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
945+
#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */
946+
#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */
947+
#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */
948+
#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */
949+
#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */
950+
#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */
951+
#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */
952+
#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */
953+
#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */
954+
#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */
955+
#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */
956+
#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */
962957

963958
/**
964959
* @}
@@ -980,7 +975,7 @@
980975
* @}
981976
*/
982977

983-
#if defined(STM32L4xx) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\
978+
#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\
984979
defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
985980
/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
986981
* @{
@@ -1005,7 +1000,7 @@
10051000
/**
10061001
* @}
10071002
*/
1008-
#endif /* STM32L4xx || STM32F7*/
1003+
#endif /* STM32L4 || STM32F7*/
10091004

10101005
/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
10111006
* @{
@@ -1190,6 +1185,9 @@
11901185
* @{
11911186
*/
11921187
#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
1188+
#define HAL_LTDC_Relaod HAL_LTDC_Reload
1189+
#define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig
1190+
#define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig
11931191
/**
11941192
* @}
11951193
*/
@@ -1625,7 +1623,11 @@
16251623

16261624
#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2
16271625
#define __HAL_I2C_GENERATE_START I2C_GENERATE_START
1626+
#if defined(STM32F1)
1627+
#define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE
1628+
#else
16281629
#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE
1630+
#endif /* STM32F1 */
16291631
#define __HAL_I2C_RISE_TIME I2C_RISE_TIME
16301632
#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD
16311633
#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST
@@ -2784,10 +2786,22 @@
27842786
#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
27852787
#define DfsdmClockSelection Dfsdm1ClockSelection
27862788
#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1
2787-
#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK
2789+
#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
27882790
#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK
27892791
#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG
27902792
#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
2793+
#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
2794+
#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1
2795+
#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1
2796+
#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1
2797+
2798+
#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1
2799+
#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2
2800+
#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1
2801+
#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2
2802+
#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2
2803+
#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2
2804+
#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1
27912805

27922806
/**
27932807
* @}
@@ -2918,6 +2932,14 @@
29182932
#define SDIO_IRQn SDMMC1_IRQn
29192933
#define SDIO_IRQHandler SDMMC1_IRQHandler
29202934
#endif
2935+
2936+
#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2)
2937+
#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef
2938+
#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef
2939+
#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef
2940+
#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef
2941+
#endif
2942+
29212943
/**
29222944
* @}
29232945
*/
@@ -3106,6 +3128,7 @@
31063128
* @{
31073129
*/
31083130
#define __HAL_LTDC_LAYER LTDC_LAYER
3131+
#define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG
31093132
/**
31103133
* @}
31113134
*/

‎system/Drivers/STM32F0xx_HAL_Driver/Inc/stm32_assert_template.h

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2,8 +2,6 @@
22
******************************************************************************
33
* @file stm32_assert.h
44
* @author MCD Application Team
5-
* @version V1.5.0
6-
* @date 04-November-2016
75
* @brief STM32 assert template file.
86
* This file should be copied to the application folder and renamed
97
* to stm32_assert.h.

‎system/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal.h

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2,8 +2,6 @@
22
******************************************************************************
33
* @file stm32f0xx_hal.h
44
* @author MCD Application Team
5-
* @version V1.5.0
6-
* @date 04-November-2016
75
* @brief This file contains all the functions prototypes for the HAL
86
* module driver.
97
******************************************************************************
@@ -532,6 +530,9 @@ void HAL_ResumeTick(void);
532530
uint32_t HAL_GetHalVersion(void);
533531
uint32_t HAL_GetREVID(void);
534532
uint32_t HAL_GetDEVID(void);
533+
uint32_t HAL_GetUIDw0(void);
534+
uint32_t HAL_GetUIDw1(void);
535+
uint32_t HAL_GetUIDw2(void);
535536
void HAL_DBGMCU_EnableDBGStopMode(void);
536537
void HAL_DBGMCU_DisableDBGStopMode(void);
537538
void HAL_DBGMCU_EnableDBGStandbyMode(void);

‎system/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc.h

Lines changed: 1 addition & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -2,8 +2,6 @@
22
******************************************************************************
33
* @file stm32f0xx_hal_adc.h
44
* @author MCD Application Team
5-
* @version V1.5.0
6-
* @date 04-November-2016
75
* @brief Header file containing functions prototypes of ADC HAL library.
86
******************************************************************************
97
* @attention
@@ -332,7 +330,6 @@ typedef struct
332330
*/
333331
#define ADC_EOC_SINGLE_CONV ((uint32_t) ADC_ISR_EOC)
334332
#define ADC_EOC_SEQ_CONV ((uint32_t) ADC_ISR_EOS)
335-
#define ADC_EOC_SINGLE_SEQ_CONV ((uint32_t)(ADC_ISR_EOC | ADC_ISR_EOS)) /*!< reserved for future use */
336333
/**
337334
* @}
338335
*/
@@ -833,8 +830,7 @@ typedef struct
833830
((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) )
834831

835832
#define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == ADC_EOC_SINGLE_CONV) || \
836-
((EOC_SELECTION) == ADC_EOC_SEQ_CONV) || \
837-
((EOC_SELECTION) == ADC_EOC_SINGLE_SEQ_CONV) )
833+
((EOC_SELECTION) == ADC_EOC_SEQ_CONV) )
838834

839835
#define IS_ADC_OVERRUN(OVR) (((OVR) == ADC_OVR_DATA_PRESERVED) || \
840836
((OVR) == ADC_OVR_DATA_OVERWRITTEN) )

‎system/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_adc_ex.h

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2,8 +2,6 @@
22
******************************************************************************
33
* @file stm32f0xx_hal_adc_ex.h
44
* @author MCD Application Team
5-
* @version V1.5.0
6-
* @date 04-November-2016
75
* @brief Header file of ADC HAL Extension module.
86
******************************************************************************
97
* @attention

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