⚠️ remove CFU CSRs (#1377)

Author: stnolting

CHANGELOG.md

@@ -29,7 +29,8 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12
 
 | Date | Version | Comment | Ticket |
 |:----:|:-------:|:--------|:------:|
-| 14.09.2025 | 1.12.1.7 | :bug: fix unaligned instruction fetch bus error; do not trigger co-processors if pending instruction-related exception | [#1367](https://github.com/stnolting/neorv32/pull/1376) |
+| 14.09.2025 | 1.12.1.8 | :warning: remove CFU CSRs (`cfureg[0..3]`) | [#1377](https://github.com/stnolting/neorv32/pull/1377) |
+| 13.09.2025 | 1.12.1.7 | :bug: fix unaligned instruction fetch bus error; do not trigger co-processors if pending instruction-related exception | [#1367](https://github.com/stnolting/neorv32/pull/1376) |
 | 13.09.2025 | 1.12.1.6 | minor RTL edits; add `Zca` ISA extension flag to `mxisa` CSR | [#1375](https://github.com/stnolting/neorv32/pull/1375) |
 | 09.09.2025 | 1.12.1.5 | TRACER: rework instruction decoding logic and add all remaining ISA extensions | [#1368](https://github.com/stnolting/neorv32/pull/1368) |
 | 05.09.2025 | 1.12.1.4 | improve TRACER's simulation-mode instruction decoding | [#1366](https://github.com/stnolting/neorv32/pull/1366) |

docs/datasheet/cpu_cfu.adoc

@@ -10,14 +10,14 @@ program memory requirements when implemented entirely in software. Some potentia
 use-cases might include:
 
 * **AI:** sub-word / vertical vector/SIMD operations like processing all four sub-bytes of a 32-bit data word individually
-* **Cryptographic:** bit substitution and permutation
+* **Cryptography:** bit substitution and permutation
 * **Communication:** data conversions like binary to gray-code
 * **Arithmetic:** BCD (binary-coded decimal) operations; multiply-add operations; shift-and-add algorithms like CORDIC or BKM
 * **Image processing:** look-up-tables for color space transformations
 * implementing instructions from **other RISC-V ISA extensions** that are not yet supported by NEORV32
 
-The NEORV32 CFU supports two different instruction formats (R3-type and R4-type; see <<_cfu_instruction_formats>>) and also
-allows to implement up to 4 CFU-internal custom control and status registers (see <<_cfu_control_and_status_registers_cfu_csrs>>).
+The NEORV32 CFU supports two different instruction formats: RISC-V R3-type (up to two source operands) and RISC-V R4-type
+(up to three source operands) instructions. See <<_cfu_instruction_formats>> for more information.
 
 .CFU Complexity
 [NOTE]
@@ -30,7 +30,7 @@ https://stnolting.github.io/neorv32/ug/#_adding_custom_hardware_modules[Adding C
 .Default CFU Hardware Example
 [TIP]
 The default CFU module (`rtl/core/neorv32_cpu_cp_cfu.vhd`) implements the _Extended Tiny Encryption Algorithm (XTEA)_
-as "real world" application example.
+as application example.
 
 
 :sectnums:
@@ -45,8 +45,8 @@ The NEORV32 CFU utilizes these two opcodes to support user-defined **R3-type** i
 1 destination register) and **R4-type** instructions (3 source registers, 1 destination register). Both instruction
 formats are compliant to the RISC-V specification.
 
-* `custom-0`: `0001011` RISC-V standard, used for NEORV32 <<_cfu_r3_type_instructions>> (3x register addresses)
-* `custom-1`: `0101011` RISC-V standard, used for NEORV32 <<_cfu_r4_type_instructions>> (4x register addresses)
+* `custom-0`: `0001011` RISC-V standard, used for NEORV32 <<_cfu_r3_type_instructions>> (3 register addresses)
+* `custom-1`: `0101011` RISC-V standard, used for NEORV32 <<_cfu_r4_type_instructions>> (4 register addresses)
 
 [TIP]
 The provided instructions formats are _predefined_ to allow an easy integration framework.
@@ -184,34 +184,6 @@ There is an example program for the CFU, which shows how to use the _default_ CF
 This example program is located in `sw/example/demo_cfu`.
 
 
-:sectnums:
-==== CFU Control and Status Registers (CFU-CSRs)
-
-The CPU provides up to four control and status registers (<<_cfureg, `cfureg*`>>) to be used within the CFU.
-These CSRs are mapped to the "custom user-mode read/write" CSR address space, which is explicitly reserved for
-platform-specific application by the RISC-V spec. For example, these CSRs can be used to pass additional operands
-to the CFU, to obtain additional results, to check processing status or to configure operation modes.
-
-.CFU CSR Access Example
-[source,c]
-----
-neorv32_cpu_csr_write(CSR_CFUREG0, 0xabcdabcd); // write data to CFU CSR 0
-uint32_t tmp = neorv32_cpu_csr_read(CSR_CFUREG3); // read data from CFU CSR 3
-----
-
-.Additional CFU-internal CSRs
-[TIP]
-If more than four CFU-internal CSRs are required the designer can implement an "indirect access mechanism" based
-on just two of the default CSRs: one CSR is used to configure the index while the other is used as alias to exchange
-data with the indexed CFU-internal CSR - this concept is similar to the RISC-V Indirect CSR Access Extension
-Specification (`Smcsrind`).
-
-.Security Considerations
-[NOTE]
-The CFU CSRs are mapped to the user-mode CSR space so software running at _any privilege level_ can access these
-CSRs.
-
-
 :sectnums:
 ==== Custom Instructions Hardware
 

docs/datasheet/cpu_csr.adoc

@@ -81,7 +81,6 @@ In the following table these CSRs are highlighted with "⚠️".
 | 0xf14 | <<_mhartid>>    | `CSR_MHARTID`    | MRO | Machine hardware thread ID
 | 0xf15 | <<_mconfigptr>> | `CSR_MCONFIGPTR` | MRO | Machine configuration pointer register
 5+^| **<<_neorv32_specific_csrs>>**
-| 0x800 .. 0x803 | <<_cfureg, `cfureg0`>> .. <<_cfureg, `cfureg3`>> | `CSR_CFUCREG0` .. `CSR_CFUCREG3` | URW | Custom CFU registers 0 to 3
 | 0xbc0 | <<_mxcsr>> | `CSR_MXCSR` | MRW | Machine status and control register
 | 0xfc0 | <<_mxisa>> | `CSR_MXISA` | MRO | Extended machine CPU ISA and extensions
 |=======================
@@ -921,24 +920,6 @@ ID of each core is unique and starts at 0 and is incremented continuously.
 All NEORV32-specific CSRs are mapped to addresses that are explicitly reserved for custom/implementation-specific use.
 
 
-[discrete]
-===== **`cfureg`**
-
-[cols="<1,<8"]
-[grid="none"]
-|=======================
-| Name        | Custom (user-defined) CFU CSRs
-| Address     | `0x800` (`cfureg0`)
-|             | `0x801` (`cfureg1`)
-|             | `0x802` (`cfureg2`)
-|             | `0x803` (`cfureg3`)
-| Reset value | `0x00000000`
-| ISA         | `Zicsr` & `Zxcfu`
-| Description | User-defined CSRs to be used within the <<_custom_functions_unit_cfu>>.
-|=======================
-
-
-{empty} +
 [discrete]
 ===== **`mxcsr`**
 

rtl/core/neorv32_cpu_alu.vhd

@@ -62,7 +62,7 @@ architecture neorv32_cpu_alu_rtl of neorv32_cpu_alu is
   -- comparator --
   signal cmp_rs1 : std_ulogic_vector(XLEN downto 0);
   signal cmp_rs2 : std_ulogic_vector(XLEN downto 0);
-  signal cmp     : std_ulogic_vector(1 downto 0); -- comparator status
+  signal cmp     : std_ulogic_vector(1 downto 0);
 
   -- operands --
   signal opa,   opb   : std_ulogic_vector(XLEN-1 downto 0);
@@ -74,22 +74,18 @@ architecture neorv32_cpu_alu_rtl of neorv32_cpu_alu is
 
   -- co-processor interface --
   type cp_data_t  is array (0 to 6) of std_ulogic_vector(XLEN-1 downto 0);
-  signal cp_result : cp_data_t; -- co-processor result
-  signal cp_valid  : std_ulogic_vector(6 downto 0); -- co-processor done
-  signal cp_shamt  : std_ulogic_vector(index_size_f(XLEN)-1 downto 0); -- shift amount
+  signal cp_result : cp_data_t;
+  signal cp_valid  : std_ulogic_vector(6 downto 0);
+  signal cp_shamt  : std_ulogic_vector(index_size_f(XLEN)-1 downto 0);
 
-  -- CSR proxy --
-  signal fpu_csr_en, cfu_csr_en : std_ulogic;
-  signal fpu_csr_we, cfu_csr_we : std_ulogic;
-  signal fpu_csr_rd, cfu_csr_rd : std_ulogic_vector(XLEN-1 downto 0);
+  -- FPU proxy --
+  signal fpu_csr_en, fpu_csr_we : std_ulogic;
+  signal fpu_csr_rd : std_ulogic_vector(XLEN-1 downto 0);
 
   -- CFU proxy --
   signal cfu_active, cfu_done, cfu_busy : std_ulogic;
   signal cfu_res : std_ulogic_vector(XLEN-1 downto 0);
 
-  -- CSR read-backs --
-  signal csr_rdata_fpu, csr_rdata_cfu : std_ulogic_vector(XLEN-1 downto 0);
-
 begin
 
   -- Comparator Unit (for conditional branches) ---------------------------------------------
@@ -150,10 +146,6 @@ begin
   -- > "cp_result" data has to be always zero unless the specific co-processor has been actually triggered
   cp_res <= cp_result(0) or cp_result(1) or cp_result(2) or cp_result(3) or cp_result(4) or cp_result(5) or cp_result(6);
 
-  -- co-processor CSR read-back --
-  -- > "csr_rdata_*" data has to be always zero unless the specific co-processor is actually being accessed
-  csr_o <= csr_rdata_fpu or csr_rdata_cfu;
-
   -- shift amount --
   cp_shamt <= opb(cp_shamt'left downto 0);
 
@@ -270,19 +262,19 @@ begin
     );
 
     -- CSR proxy --
-    fpu_csr_en    <= '1' when (ctrl_i.csr_addr(11 downto 2) = csr_fflags_c(11 downto 2)) else '0';
-    fpu_csr_we    <= fpu_csr_en and ctrl_i.csr_we;
-    csr_rdata_fpu <= fpu_csr_rd when (fpu_csr_en = '1') else (others => '0');
+    fpu_csr_en <= '1' when (ctrl_i.csr_addr(11 downto 2) = csr_fflags_c(11 downto 2)) else '0';
+    fpu_csr_we <= fpu_csr_en and ctrl_i.csr_we;
+    csr_o      <= fpu_csr_rd when (fpu_csr_en = '1') else (others => '0');
   end generate;
 
   neorv32_cpu_cp_fpu_inst_false:
   if not RISCV_ISA_Zfinx generate
-    fpu_csr_en    <= '0';
-    fpu_csr_we    <= '0';
-    fpu_csr_rd    <= (others => '0');
-    csr_rdata_fpu <= (others => '0');
-    cp_result(3)  <= (others => '0');
-    cp_valid(3)   <= '0';
+    fpu_csr_en   <= '0';
+    fpu_csr_we   <= '0';
+    fpu_csr_rd   <= (others => '0');
+    csr_o        <= (others => '0');
+    cp_result(3) <= (others => '0');
+    cp_valid(3)  <= '0';
   end generate;
 
 
@@ -293,33 +285,23 @@ begin
     neorv32_cpu_cp_cfu_inst: entity neorv32.neorv32_cpu_cp_cfu
     port map (
       -- global control --
-      clk_i       => clk_i,                          -- global clock, rising edge
-      rstn_i      => rstn_i,                         -- global reset, low-active, async
+      clk_i    => clk_i,                          -- global clock, rising edge
+      rstn_i   => rstn_i,                         -- global reset, low-active, async
       -- operation control --
-      start_i     => ctrl_i.alu_cp_cfu,              -- operation trigger/strobe
-      active_i    => cfu_active,                     -- operation in progress, CPU is waiting for CFU
-      -- CSR interface --
-      csr_we_i    => cfu_csr_we,                     -- write enable
-      csr_addr_i  => ctrl_i.csr_addr(1 downto 0),    -- address
-      csr_wdata_i => ctrl_i.csr_wdata,               -- write data
-      csr_rdata_o => cfu_csr_rd,                     -- read data
+      start_i  => ctrl_i.alu_cp_cfu,              -- operation trigger/strobe
+      active_i => cfu_active,                     -- operation in progress, CPU is waiting for CFU
       -- operands --
-      rtype_i     => ctrl_i.ir_opcode(5),            -- instruction type (R3-type or R4-type)
-      funct3_i    => ctrl_i.ir_funct3,               -- "funct3" bit-field from custom instruction word
-      funct7_i    => ctrl_i.ir_funct12(11 downto 5), -- "funct7" bit-field from custom instruction word
-      rs1_i       => rs1_i,                          -- rf source 1
-      rs2_i       => rs2_i,                          -- rf source 2
-      rs3_i       => rs3_i,                          -- rf source 3
+      rtype_i  => ctrl_i.ir_opcode(5),            -- instruction type (R3-type or R4-type)
+      funct3_i => ctrl_i.ir_funct3,               -- "funct3" bit-field from custom instruction word
+      funct7_i => ctrl_i.ir_funct12(11 downto 5), -- "funct7" bit-field from custom instruction word
+      rs1_i    => rs1_i,                          -- rf source 1
+      rs2_i    => rs2_i,                          -- rf source 2
+      rs3_i    => rs3_i,                          -- rf source 3
       -- result and status --
-      result_o    => cfu_res,                        -- operation result
-      valid_o     => cfu_done                        -- result valid, operation done; set one cycle before result_o is valid
+      result_o => cfu_res,                        -- operation result
+      valid_o  => cfu_done                        -- result valid, operation done; set one cycle before result_o is valid
     );
 
-    -- CSR proxy --
-    cfu_csr_en    <= '1' when (ctrl_i.csr_addr(11 downto 2) = csr_cfureg0_c(11 downto 2)) else '0';
-    cfu_csr_we    <= cfu_csr_en and ctrl_i.csr_we;
-    csr_rdata_cfu <= cfu_csr_rd when (cfu_csr_en = '1') else (others => '0');
-
     -- response proxy --
     cfu_arbiter: process(rstn_i, clk_i)
     begin
@@ -346,16 +328,12 @@ begin
 
   neorv32_cpu_cp_cfu_inst_false:
   if not RISCV_ISA_Zxcfu generate
-    cfu_csr_en    <= '0';
-    cfu_csr_we    <= '0';
-    cfu_done      <= '0';
-    cfu_res       <= (others => '0');
-    cfu_csr_rd    <= (others => '0');
-    csr_rdata_cfu <= (others => '0');
-    cfu_busy      <= '0';
-    cfu_active    <= '0';
-    cp_result(4)  <= (others => '0');
-    cp_valid(4)   <= '0';
+    cfu_done     <= '0';
+    cfu_res      <= (others => '0');
+    cfu_busy     <= '0';
+    cfu_active   <= '0';
+    cp_result(4) <= (others => '0');
+    cp_valid(4)  <= '0';
   end generate;
 
 

rtl/core/neorv32_cpu_control.vhd

@@ -652,10 +652,6 @@ begin
     -- ------------------------------------------------------------
     case csr_addr_v is
 
-      -- NEORV32-specific user-mode CFU CSRs --
-      when csr_cfureg0_c | csr_cfureg1_c | csr_cfureg2_c | csr_cfureg3_c =>
-        csr_valid(2) <= bool_to_ulogic_f(RISCV_ISA_Zxcfu); -- available if CFU implemented
-
       -- floating-point-unit CSRs --
       when csr_fflags_c | csr_frm_c | csr_fcsr_c =>
         csr_valid(2) <= bool_to_ulogic_f(RISCV_ISA_Zfinx); -- available if FPU implemented