Terminal Program for Linux

[srvedulageth]

Hi, I cloned neorv32 on Ubuntu Linux. I also have Vivado installed on my Linux and i am able to synthesize and implement for xc7A100 part.
Twos issues:

1. I want to connect to UART. What is the cable needed? I think we need UART <----> USB cable. Can you suggest the cable required?
2. Terminal Program: which terminal program program i should use?

[srvedulageth]

It appears i just need Pmod USBUART: USB to UART Interface which is available for around 14$s from Digilent.
Is this correct?

[stnolting]

Hi, I cloned neorv32 on Ubuntu Linux. I also have Vivado installed on my Linux and i am able to synthesize and implement for xc7A100 part.

That's great! 👍

I want to connect to UART. What is the cable needed? I think we need UART <----> USB cable. Can you suggest the cable required?

Any USB UART bridge should do the job. But I recommend you use an (original) FTDI-based.

Right now I am using this brdige: https://docs.espressif.com/projects/esp-iot-solution/en/latest/hw-reference/ESP-Prog_guide.html
The cool thing is that this is a dual-channel FTDI chip. So you can use both UART and JTAG for the on-chip debugger with one USB port.

Terminal Program: which terminal program program i should use?

That's a good question... For Linux I can recommend minicom or just putty.

It appears i just need Pmod USBUART: USB to UART Interface which is available for around 14$s from Digilent.
Is this correct?

That's a nice one. But there are other FTDI-based adapters out there that are a bit cheaper.

[srvedulageth]

Hi, Thank you.

> That's a nice one. But there are other FTDI-based adapters out there that are a bit cheaper.

If possible, could you please send a link. Thank you. --Vedula. On Friday, July 18, 2025 at 11:56:51 AM PDT, stnolting ***@***.***> wrote: Hi, I cloned neorv32 on Ubuntu Linux. I also have Vivado installed on my Linux and i am able to synthesize and implement for xc7A100 part. That's great! 👍 I want to connect to UART. What is the cable needed? I think we need UART <----> USB cable. Can you suggest the cable required? Any USB UART bridge should do the job. But I recommend you use an (original) FTDI-based. Right now I am using this brdige: https://docs.espressif.com/projects/esp-iot-solution/en/latest/hw-reference/ESP-Prog_guide.html The cool thing is that this is a dual-channel FTDI chip. So you can use both UART and JTAG for the on-chip debugger with one USB port. Terminal Program: which terminal program program i should use? That's a good question... For Linux I can recommend minicom or just putty. It appears i just need Pmod USBUART: USB to UART Interface which is available for around 14$s from Digilent. Is this correct? That's a nice one. But there are other FTDI-based adapters out there that are a bit cheaper. — Reply to this email directly, view it on GitHub, or unsubscribe. You are receiving this because you authored the thread.Message ID: ***@***.***>

[stnolting]

If possible, could you please send a link.

I cannot guarantee that it will be available at your location.
Just check some local electronics sites. I bought mine on ebay.

[srvedulageth]

I just need the part nymber. I will look around. Tq

[stnolting]

I would recommend this: https://eu.mouser.com/ProductDetail/Espressif-Systems/ESP-PROG?qs=0lSvoLzn4L9lCAjJ8r9cdg%3D%3D

This gives you a UART and at the same time a JTAG port for the on-chip debugger - all via a single USB connection.

[srvedulageth]

Hi Stephan,

I just ordered this part.
Is it possible to share a small image how you have connected this to Arty A7 100T?

--Vedula.

[stnolting]

You can find the pinout of the ESP board here: https://docs.espressif.com/projects/esp-iot-solution/en/latest/hw-reference/ESP-Prog_guide.html

Export the processor's JTAG signals via some pin headers (like the PMODs) and wire-up the ESP board:

ESP_TMS -> jtag_tms_i
ESP_TCK -> jtag_tck_i
ESP_TDO -> jtag_tdo_o
ESP_TDI -> jtag_tdi_i

Btw, you can use the USB-UART bridge of the arty board - so no need to add external wires for that.

[srvedulageth]

> Btw, you can use the USB-UART bridge of the arty board - so no need to add external wires for that.

Exactly. I ordered this add-on card as you suggested. https://www.mouser.com/ProductDetail/Espressif-Systems/ESP-PROG?qs=0lSvoLzn4L9lCAjJ8r9cdg%3D%3D I should receive it by Wednesday/USA/PST. Please see the attachment. This is the picture of Arty A7-100. I want to know how this ESP board mates with Arty A7-100? --Vedula On Monday, July 21, 2025 at 08:46:28 AM PDT, stnolting ***@***.***> wrote: You can find the pinout of the ESP board here: https://docs.espressif.com/projects/esp-iot-solution/en/latest/hw-reference/ESP-Prog_guide.html Export the processor's JTAG signals via some pin headers (like the PMODs) and wire-up the ESP board: ESP_TMS -> jtag_tms_i ESP_TCK -> jtag_tck_i ESP_TDO -> jtag_tdo_o ESP_TDI -> jtag_tdi_i Btw, you can use the USB-UART bridge of the arty board - so no need to add external wires for that. — Reply to this email directly, view it on GitHub, or unsubscribe. You are receiving this because you authored the thread.Message ID: ***@***.***>

[srvedulageth]

When I look at the XDC of the Arty A7 100, it looks like the FPGAs are pin-compatible. So maybe you can just re-use my XDC snippet.

Response>> Yes i can use. I checked. Tq.

[srvedulageth]

I am going get mating part for A7 100 (https://www.mouser.com/ProductDetail/Espressif-Systems/ESP-PROG?qs=0lSvoLzn4L9lCAjJ8r9cdg%3D%3D) today or so.

where will get these jumpers from? Arrow Electronics?

[srvedulageth]

I ordered these

(https://www.amazon.com/dp/B0D56V6S8M?ref=fed_asin_title&th=1)

[srvedulageth]

I am curious. I think i don't i need any Pmod usb2uart cards right away i think. I THINK.

I am seeing a "Shared USB JTAG / UART port"

May be i can upload bitstream of Neorv32 (already generated) and connect to uart using minicom.

Is this correct?

[stnolting]

That's right. The Arty boards have a dual-channel FTDI chip: one channel for loading the bitstream and another one for UART.

[srvedulageth]

Yes i am able to see the banner NeorV32 ... via uart yesterday.
I am building a riscv tool chain now. Tq

How about debuuger?
Do i really need this ESP board? I just got it delivered.

[srvedulageth]

1. Very good news.
   I am able to successfully generate bit stream and load executable for demo_blink_led. Leds are blinking.
2. One observation is i used riscv64- ; 64 bit version. still worked.

Thank you.

I did not use the new ESP board i got so far.

I want to try the debugger. Do i need that board?

Thank you all

[stnolting]

I am able to successfully generate bit stream and load executable for demo_blink_led. Leds are blinking.

I'm glad to hear that! 🚀

One observation is i used riscv64- ; 64 bit version. still worked.

The 64-bit toolchains can also generate code for 32-bit platforms if MARCH=rv32.

I want to try the debugger. Do i need that board?

Short answer: yes. 😅

Long answer: you could also use the JTAG interface of the FPGA (that is used for loading the bitstream). But that would require a rather complex "proxy logic".

[srvedulageth]

Hi
I want to try with debugger. do you have a xdc file and tcl file (which compiles OCD vhd file) corresponding to this?
You do have a xdc and tcl files for bot loader in arty-a7-test--setup dir.

--Vedula.

[stnolting]

Unfortunately, I don't have an Arty-100 board, and in https://github.com/stnolting/neorv32-setups/tree/main/vivado/arty-a7-test-setup we only have a TCL script for the 35 version, but you could use that as a starting point (pin-compatible?).

For the on-chip dbeugger (OCD) you can start with this test setup: https://github.com/stnolting/neorv32/blob/main/rtl/test_setups/neorv32_test_setup_on_chip_debugger.vhd

[srvedulageth]

WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.

vivado.log
create_project-tcl.log
arty_a7_test_setup-xdc.log

Hi, is this fine? I am also seeing 47 warnings from DRC.

[stnolting]

I cannot test it over here, but your XDC and TCL files look pretty good so far.

WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.

That shouldn't be a problem at first. Maybe there's just something wrong with the power model settings. However, the corresponding report should contain information about which net causes this warning.

[srvedulageth]

There are two usb connectors, one on arty 7 and one on

Do i need to connect both to two usb slots in my laptop? and then use one for programming and one for debugging?

I am using gtkterm and i need to essentially open two of these and connect one to program port and the other to debugging port right?

[stnolting]

That looks good! However, you should also connect ground from the ESP adapter and the PMOD port (even though they are essentially connected via USB).

Do i need to connect both to two usb slots in my laptop? and then use one for programming and one for debugging?

Right. The Arty's USB port provides the FPGA programming port and a UART. The USB port on the ESP board is used for the on-chip debugger.

(you can also use the second channel on the ESP board for the UART connection)

I am using gtkterm and i need to essentially open two of these and connect one to program port and the other to debugging port right?

You just need one instance of GTKterm to connect to the processor's UART interface. The JTAG port of the on-chip debugger will be used by openOCD.

[srvedulageth]

This is what i did.

1. cp ../../neorv32/sw/openocd/*.cfg .
2. cp openocd_neorv32.cfg openocd.cfg
3. openocd

openocd
Open On-Chip Debugger 0.12.0
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html

---

NEORV32 single-core openOCD configuration

---

Info : clock speed 2000 kHz
Error: JTAG scan chain interrogation failed: all zeroes
Error: Check JTAG interface, timings, target power, etc.
Error: Trying to use configured scan chain anyway...
Error: neorv32.cpu: IR capture error; saw 0x1f not 0x01
Warn : Bypassing JTAG setup events due to errors
Error: dtmcontrol is 0. Check JTAG connectivity/board power.
Warn : target neorv32.cpu examination failed
Info : starting gdb server for neorv32.cpu on 3333
Info : Listening on port 3333 for gdb connections
openocd: src/target/riscv/riscv-011.c:435: dbus_scan

I checked connections and power seems to be there as u can see power led lit up.

What could be the issue?

[stnolting]

This is your XDC file, right?

## Pmod Header JB (used as JTAG Extensions)
set_property -dict { PACKAGE_PIN E15  IOSTANDARD LVCMOS33 } [get_ports { jtag_tck_i }]; #IO_0_15 Sch=jb[1]
set_property -dict { PACKAGE_PIN E16  IOSTANDARD LVCMOS33 } [get_ports { jtag_tdi_i }]; #IO_L4P_T0_15 Sch=jb[2]
set_property -dict { PACKAGE_PIN D15  IOSTANDARD LVCMOS33 } [get_ports { jtag_tdo_o }]; #IO_L4N_T0_15 Sch=jb[3]
set_property -dict { PACKAGE_PIN C15  IOSTANDARD LVCMOS33 } [get_ports { jtag_tms_i }]; #IO_L6P_T0_15 Sch=jb[4]

So the PMOD's right-most pin is E15 and the left-most pin is C15 and this should be the front-side of your PMOD:

VCC | GND | tms_i | tdo_o | tdi_i | tck_i
VCC | GND |   -   |   -   |   -   |   - 

[stnolting]

Here is the pinout of the ESP prog:

So you need to connect:

• ESP_TMS -> tms_i
• ESP_TCK -> tck_i
• ESP_TDO <- tdo_o
• ESP_TDI -> tdi_i

[srvedulageth]

arty_a7_test_setup_xdc.log

This is my xdc file. I made changes from the time i sent as i want to align (matching order w.r.t. to EPS board, tms, tck, tdo, tdi

[srvedulageth]

Pmod Header JB (used as JTAG Extensions)

set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { jtag_tms_i }]; #IO_0_15 Sch=jb[1]
set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { jtag_tck_i }]; #IO_L4P_T0_15 Sch=jb[2]
set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { jtag_tdo_o }]; #IO_L4N_T0_15 Sch=jb[3]
set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { jtag_tdi_i }]; #IO_L6P_T0_15 Sch=jb[4]

VCC | GND | tdi_i | tdo_o | tck_i | tms_i
VCC | GND | - | - | - | -

[srvedulageth]

I think i did not reimplement after changing xdc file :)

Let me try that.

[srvedulageth]

openocd
Open On-Chip Debugger 0.12.0
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html

---

NEORV32 single-core openOCD configuration

---

Info : clock speed 2000 kHz
Info : JTAG tap: neorv32.cpu tap/device found: 0x00000001 (mfg: 0x000 (), part: 0x0000, ver: 0x0)
Info : datacount=1 progbufsize=2
Info : Disabling abstract command reads from CSRs.
Info : Examined RISC-V core; found 1 harts
Info : hart 0: XLEN=32, misa=0x40901104
Info : starting gdb server for neorv32.cpu on 3333
Info : Listening on port 3333 for gdb connections
Authentication passed.
Info : JTAG tap: neorv32.cpu tap/device found: 0x00000001 (mfg: 0x000 (), part: 0x0000, ver: 0x0)
Target RESET and HALTED. Ready for remote connections.
Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections

WORKED!!!!
Thank you

[stnolting]

I'm glad to hear that!