Certus-NX port

[babryceAPL]

Based on the Icebreaker memory design and the DMEM and IMEM files I have tried to mirror that into the large block RAM for the Certus-NX. Compiles, bootloader runs, but uploads for exe that run with the system inferred in distributed RAM fail:

Example:

ERROR_CHECKSUM
ERROR_EXCEPTION 0x00000003 0xffe00a84 0x00100073 0x00000000

I tired it a few ways, with the Reg buffer and without, more like the original Icebreaker code for the ack and trying to stick to the head code as of today. I will keep thinking but I am a bit puzzled at this point, it may be very obvious to someone more familiar with this project.

A to B is: everything inferred from the base project works but uses most distributed block RAM, swapping DMEM to below boots but breaks in the way described. Superficially there looks to be plenty of timing slack.

Here is the DMEM code:

-- ================================================================================ --
-- NEORV32 SoC - Processor-Internal Data Memory (DMEM)                              --
-- -------------------------------------------------------------------------------- --
-- The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32              --
-- Copyright (c) NEORV32 contributors.                                              --
-- Copyright (c) 2020 - 2025 Stephan Nolting. All rights reserved.                  --
-- Licensed under the BSD-3-Clause license, see LICENSE for details.                --
-- SPDX-License-Identifier: BSD-3-Clause                                            --
-- ================================================================================ --

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library neorv32;
use neorv32.neorv32_package.all;

library lfd2nx;
use lfd2nx.components.all;

entity neorv32_dmem is
  generic (
    MEM_SIZE  : natural; -- memory size in bytes, has to be a power of 2, min 4
    OUTREG_EN : boolean  -- implement output register stage
  );
  port (
    clk_i     : in  std_ulogic; -- global clock line
    rstn_i    : in  std_ulogic; -- async reset, low-active
    bus_req_i : in  bus_req_t;  -- bus request
    bus_rsp_o : out bus_rsp_t   -- bus response
  );
end neorv32_dmem;

architecture neorv32_dmem_rtl of neorv32_dmem is

  -- auto-configuration --
  constant awidth_c  : natural := index_size_f(MEM_SIZE/4); -- word address width
  constant latency_c : natural := cond_sel_natural_f(OUTREG_EN, 2, 1); -- memory latency

  -- local signals --
  signal rdata : std_ulogic_vector(31 downto 0);
  signal wack  : std_ulogic;
  signal rden  : std_ulogic_vector(1 downto 0);
  --signal rden : std_logic;
  signal en    : std_ulogic_vector(3 downto 0);
  
  signal mem_cs : std_ulogic;
  
  
    -- SPRAM signals --
  signal spram_clk   : std_logic;
  signal spram_addr  : std_logic_vector(13 downto 0);
  signal spram_di    : std_logic_vector(31 downto 0);
  signal spram_do    : std_logic_vector(31 downto 0);
  signal spram_be    : std_logic_vector(3 downto 0);
  signal spram_we    : std_logic;
  --signal spram_pwr_n : std_logic;
  signal spram_cs    : std_logic;

begin

  mem_cs <= bus_req_i.stb;

  -- Memory Core ----------------------------------------------------------------------------
  -- -------------------------------------------------------------------------------------------
	dmem_spram_inst : SP512K
	--generic map(
	--OUTREG => "OUT_REG"
	--)
	port map (
	DI       => spram_di,    
	AD       => spram_addr, 	
	CLK      => spram_clk,  
	CE       => '1', 
	WE       => spram_we,   
	CS       => spram_cs,   
	RSTOUT   => '0',
	CEOUT    => '1',
	BYTEEN_N => spram_be,	
	DO      => spram_do 
	);

	spram_addr <= std_logic_vector(bus_req_i.addr(13+2 downto 2));
	spram_di <= std_logic_vector(bus_req_i.data);
	spram_we <= '1' when (bus_req_i.rw = '1') else '0'; -- global write enable
	spram_clk <= std_logic(clk_i);
	spram_cs  <= std_logic(mem_cs);
	spram_be <= not en;
	rdata <= std_ulogic_vector(spram_do);

  -- byte-wise enable --
  en <= bus_req_i.ben when (bus_req_i.stb = '1') else (others => '0');


  -- Bus Handshake --------------------------------------------------------------------------
  -- -------------------------------------------------------------------------------------------
  bus_handshake: process(rstn_i, clk_i)
  begin
    if (rstn_i = '0') then
      wack <= '0';
      rden <= (others => '0');
    elsif rising_edge(clk_i) then
      wack <= bus_req_i.stb and bus_req_i.rw;
      rden <= rden(0) & (bus_req_i.stb and (not bus_req_i.rw));
    end if;
  end process bus_handshake;

  bus_rsp_o.data <= rdata when (rden(latency_c-1) = '1') else (others => '0'); -- output gate
  bus_rsp_o.err  <= '0'; -- no access error possible
  bus_rsp_o.ack  <= rden(latency_c-1) or wack;
  
  
  --buffer_ff: process(clk_i)
  --begin
    --if rising_edge(clk_i) then
      --bus_rsp_o.ack <= mem_cs;
      --rden          <= bus_req_i.stb and (not bus_req_i.rw);
    --end if;
  --end process buffer_ff;

   --no access error possible --
  --bus_rsp_o.err <= '0';

   --output gate --
  --bus_rsp_o.data <= rdata when (rden = '1') else (others => '0');


end neorv32_dmem_rtl;

[stnolting]

The code looks good at first glance. I've never worked with these FPGAs myself... Do you perhaps have a link to the description of the memory primitives?

[stnolting]

You are using Lattice Radiant, right?

In your synthesis setup, do you use Lattice Synthesis Engine (LSE) or Sinplify Pro? Maybe you can try switching to the other synthesis engine.

[babryceAPL]

Yeah Radiant. Was using Synopsis but can try LSE. But if the RTL looks right then it is just the route/place really and that should always be Lattice I think.

[babryceAPL]

I was able to get it to work. I used the block RAM wizard and made a custom memory, then looked at the physical level in the routing to see what the difference was between my primitive inferred code and the high level wrapper based code was.

I failed to set: ECC_BYTE_SEL => "BYTE_EN" in the parameter list. In the primitive doc shown above in the image it isn't super clear on first reading but that was the issue. The RTL actually looks quite messy (above) and confused on second look in the Lattice viewer but looks exactly like the code in the Synopsis one (output gate). Synth with LSE yields something that looks right in the Lattice RTL viewer. I am willing to live with that minor mystery. The issue was just the parameter.

-- ================================================================================ --
-- NEORV32 SoC - Processor-Internal Data Memory (DMEM)                              --
-- -------------------------------------------------------------------------------- --
-- The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32              --
-- Copyright (c) NEORV32 contributors.                                              --
-- Copyright (c) 2020 - 2025 Stephan Nolting. All rights reserved.                  --
-- Licensed under the BSD-3-Clause license, see LICENSE for details.                --
-- SPDX-License-Identifier: BSD-3-Clause                                            --
-- ================================================================================ --

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library neorv32;
use neorv32.neorv32_package.all;

library lfd2nx;
use lfd2nx.components.all;

entity neorv32_dmem is
  generic (
    MEM_SIZE  : natural; -- memory size in bytes, has to be a power of 2, min 4
    OUTREG_EN : boolean  -- implement output register stage
  );
  port (
    clk_i     : in  std_ulogic; -- global clock line
    rstn_i    : in  std_ulogic; -- async reset, low-active
    bus_req_i : in  bus_req_t;  -- bus request
    bus_rsp_o : out bus_rsp_t   -- bus response
  );
end neorv32_dmem;

architecture neorv32_dmem_rtl of neorv32_dmem is

  -- auto-configuration --
  constant awidth_c  : natural := index_size_f(MEM_SIZE/4); -- word address width
  constant latency_c : natural := cond_sel_natural_f(OUTREG_EN, 2, 1); -- memory latency
  constant reg_ram_c : string := cond_sel_string_f(OUTREG_EN, "OUT_REG", "NO_REG"); -- select reg or no reg

  -- local signals --
  signal rdata : std_ulogic_vector(31 downto 0);
  signal wack  : std_ulogic;
  signal rden  : std_ulogic_vector(1 downto 0);
  signal en    : std_ulogic_vector(3 downto 0);
  
  -- SPRAM signals --
  signal spram_clk   : std_logic;
  signal spram_addr  : std_logic_vector(13 downto 0);
  signal spram_di    : std_logic_vector(31 downto 0);
  signal spram_do    : std_logic_vector(31 downto 0);
  signal spram_be    : std_logic_vector(3 downto 0);
  signal spram_we    : std_logic;
  signal spram_cs    : std_logic;
  

begin  

  -- Memory Core ----------------------------------------------------------------------------
  -- -------------------------------------------------------------------------------------------
  dmem_spram_inst : SP512K
  generic map(
  OUTREG => reg_ram_c,
  ECC_BYTE_SEL => "BYTE_EN"
  )
  port map(
    DI       => spram_di,    
    AD       => spram_addr, 	
    CLK      => spram_clk,  
    CE       => '1', 
    WE       => spram_we,   
    CS       => spram_cs,   
    RSTOUT   => '0',
    CEOUT    => '1',
    BYTEEN_N => spram_be,	
    DO       => spram_do 
  );
	
  spram_addr <= std_logic_vector(bus_req_i.addr(13+2 downto 2));
  spram_di <= std_logic_vector(bus_req_i.data);
  spram_we <= '1' when (bus_req_i.rw = '1') else '0'; -- global write enable
  spram_clk <= std_logic(clk_i);
  spram_cs  <= std_logic(bus_req_i.stb);
  spram_be <= not en;
  rdata <= std_ulogic_vector(spram_do);

  -- byte-wise enable --
  en <= bus_req_i.ben when (bus_req_i.stb = '1') else (others => '0');

  -- Bus Handshake --------------------------------------------------------------------------
  -- -------------------------------------------------------------------------------------------
  bus_handshake: process(rstn_i, clk_i)
  begin
    if (rstn_i = '0') then
      wack <= '0';
      rden <= (others => '0');
    elsif rising_edge(clk_i) then
      wack <= bus_req_i.stb and bus_req_i.rw;
      rden <= rden(0) & (bus_req_i.stb and (not bus_req_i.rw));
    end if;
  end process bus_handshake;

  bus_rsp_o.data <= rdata when (rden(latency_c-1) = '1') else (others => '0'); -- output gate 
  bus_rsp_o.err  <= '0'; -- no access error possible
  bus_rsp_o.ack  <= rden(latency_c-1) or wack;

end neorv32_dmem_rtl;

Is an example of working code for a 64k DMEM on any Certus-NX and similar parts:

• LFCPNX
• LFD2NX
• LFD2NX-35
• LFD2NX-65
• LFMXO5
• LFMXO5-35T
• LFMXO5-65T
• LIFCL
• UT24C
• UT24CP

[stnolting]

Great to hear!

I used the block RAM wizard and made a custom memory, then looked at the physical level in the routing to see what the difference was between my primitive inferred code and the high level wrapper based code was.

That's clever! 😉

How big are theses memory primitives actually? 64kB?

[babryceAPL]

2^14 words of 32 bit for the LRAM in all of the devices listed. Same depth as the other Lattice part just wider (32 vs 16) so only one block involved instead of your parallel code for the other.