Want to add OCD to the SoC i am working on.

[srvedulageth]

Hi,

1. I am working on an SoC based on all OpenCore cores like ZAP processor etc.
2. Want to add OCD for this.

Can someone guide me please.

--Vedula.

[anntnzrb]

For NEORV32-based SoCs: enable OCD with OCD_EN => true generic in your top-level instantiation and wire JTAG signals (jtag_tck_i, jtag_tdi_i, jtag_tdo_o, jtag_tms_i). See docs/userguide/using_ocd.adoc for OpenOCD setup.

For non-NEORV32 cores (like ZAP): the NEORV32 OCD is tightly coupled to its CPU architecture and not directly portable. You'll need to implement your own RISC-V Debug Spec v0.13/1.0 compliant modules - use rtl/core/neorv32_debug_dm.vhd and rtl/core/neorv32_debug_dtm.vhd as reference implementations.

[stnolting]

Good point!

Actually, the NEORV33 DTM is independent of the rest of the OCD and the interface (mostly) complies to the RISC-V debug specs.