DecimationFactor, XRFDC_FAB_CLK_DIVx

[jacobhot]

Hello!
First of all thank you very much for this great example!
I would like to ask about the sample rate setting. The sample rate is set using two values ​​(DecimationFactor, XRFDC_FAB_CLK_DIVx). There are several sample rates to choose from. I tried adding another one with a decimation of 20 (sr=245760000.0) but I don't know what value to choose for XRFDC_FAB_CLK_DIVx. In addition, in Pynq I found that this value can only be 2,4,8,16. I don't understand how it is possible to enter values ​​of 3,5 here as used in this example.
Many thanks for help,
Jakub

[marsiau]

Hey,

Huge apologies for a very late reply.

The XRFDC_FAB_CLK_DIVx values come from embeddedsw rfdc driver line 964. 1, 2, 4, 8 and 16 are the actual clock decimation rates, but they get set using their index: 1, 2, 3, 4 and 5. Very confusing indeed :D

I would recommend adjusting the actual sampling rate of the RF-ADCs and setting a matching RF-DC output fabric clock instead of enabling x20 decimation.

Although using XRFDC_FAB_CLK_DIVx is a neat trick it only enables 5 matching runtime configurable decimation rates. I'm currently investigating using a reprogrammable clock wizard to overcome this issue.

Cheers,
Marius.

[jacobhot]

Hello Marius!
no problem with the late reply. I also have a lot of things to do. Thank you very much for the recommendation and for the explanation. I will try it out
Best regards
Jakub