TEMP: try including stage0 target

Author: nhtyy

compiler/rustc_target/src/spec/targets/riscv32im_succinct_zkvm_elf.rs

@@ -5,7 +5,7 @@ pub(crate) fn target() -> Target {
         data_layout: "e-m:e-p:32:32-i64:64-n32-S128".into(),
         llvm_target: "riscv32".into(),
         metadata: crate::spec::TargetMetadata {
-            description: Some("RISC Zero's zero-knowledge Virtual Machine (RV32IM ISA)".into()),
+            description: Some("Succincts zero-knowledge Virtual Machine (RV32IM ISA)".into()),
             tier: Some(3),
             host_tools: Some(false),
             std: None, // ?

src/bootstrap/src/core/sanity.rs

@@ -33,7 +33,7 @@ pub struct Finder {
 //
 // Targets can be removed from this list once they are present in the stage0 compiler (usually by updating the beta compiler of the bootstrap).
 const STAGE0_MISSING_TARGETS: &[&str] = &[
-    // just a dummy comment so the list doesn't get onelined
+    "riscv32im-succinct-zkvm-elf",
 ];
 
 /// Minimum version threshold for libstdc++ required when using prebuilt LLVM