fix(data): merge definitions for ld/sd (riscv-software-src#869)

`ld` and `sd` are defined for both "I" extension (RV64) as well as
"Zilsd" extension (RV32). They are currently defined separately for each
extension.

Merge them.

Fixes riscv-software-src#821

Author: ThinkOpenly

backends/instructions_appendix/all_instructions.golden.adoc

@@ -14920,17 +14920,34 @@ Assembly::
 ld xd, imm(xs1)
 
 Encoding::
+[NOTE]
+This instruction has different encodings in RV32 and RV64
+
+RV32::
+[wavedrom, ,svg,subs='attributes',width="100%"]
+....
+{"reg":[{"bits":7,"name": 0x3,"type":2},{"bits":5,"name": "xd != {1,3,5,7,9,11,13,15,17,19,21,23,25,27,29,31}","type":4},{"bits":3,"name": 0x3,"type":2},{"bits":5,"name": "xs1","type":4},{"bits":12,"name": "imm","type":4}]}
+....
+
+RV64::
 [wavedrom, ,svg,subs='attributes',width="100%"]
 ....
 {"reg":[{"bits":7,"name": 0x3,"type":2},{"bits":5,"name": "xd","type":4},{"bits":3,"name": 0x3,"type":2},{"bits":5,"name": "xs1","type":4},{"bits":12,"name": "imm","type":4}]}
 ....
 
 Description::
-Load 64 bits of data into register `xd` from an
+For RV64, load 64 bits of data into register `xd` from an
 address formed by adding `xs1` to a signed offset.
+<% if ext?(:Zilsd) %>
+For RV32, Loads a 64-bit value into registers xd and xd+1.
+The effective address is obtained by adding
+register xs1 to the sign-extended 12-bit offset.
+<% end %>
 
 
 Decode Variables::
+*RV32:*
+
 [width="100%", cols="1,2", options="header"]
 |===
 |Variable Name |Location
@@ -14939,50 +14956,23 @@ Decode Variables::
 |xd |$encoding[11:7]
 |===
 
-Included in::
-[options="autowrap,autowidth"]
-|===
-| Extension | Version
-
-| *I* | ~> 2.1.0
-
-|===
-
-
-[#udb:doc:inst:ld]
-== ld
-
-Synopsis::
-Load doubleword to even/odd register pair
-
-Assembly::
-ld xd, offset(xs1)
-
-Encoding::
-[wavedrom, ,svg,subs='attributes',width="100%"]
-....
-{"reg":[{"bits":7,"name": 0x3,"type":2},{"bits":5,"name": "xd != {1,3,5,7,9,11,13,15,17,19,21,23,25,27,29,31}","type":4},{"bits":3,"name": 0x3,"type":2},{"bits":5,"name": "xs1","type":4},{"bits":12,"name": "imm","type":4}]}
-....
-
-Description::
-Loads a 64-bit value into registers xd and xd+1. The effective address is obtained by adding
-register xs1 to the sign-extended 12-bit offset.
-
+*RV64:*
 
-Decode Variables::
 [width="100%", cols="1,2", options="header"]
 |===
 |Variable Name |Location
-|xd |$encoding[11:7]
-|xs1 |$encoding[19:15]
 |imm |$encoding[31:20]
+|xs1 |$encoding[19:15]
+|xd |$encoding[11:7]
 |===
 
 Included in::
 [options="autowrap,autowidth"]
 |===
 | Extension | Version
 
+| *I* | ~> 2.1.0
+
 | *Zilsd* | ~> 1.0
 
 |===
@@ -17237,69 +17227,57 @@ Assembly::
 sd xs2, imm(xs1)
 
 Encoding::
+[NOTE]
+This instruction has different encodings in RV32 and RV64
+
+RV32::
+[wavedrom, ,svg,subs='attributes',width="100%"]
+....
+{"reg":[{"bits":7,"name": 0x23,"type":2},{"bits":5,"name": "imm[4:0]","type":4},{"bits":3,"name": 0x3,"type":2},{"bits":5,"name": "xs1","type":4},{"bits":5,"name": "xs2 != {1,3,5,7,9,11,13,15,17,19,21,23,25,27,29,31}","type":4},{"bits":7,"name": "imm[11:5]","type":4}]}
+....
+
+RV64::
 [wavedrom, ,svg,subs='attributes',width="100%"]
 ....
 {"reg":[{"bits":7,"name": 0x23,"type":2},{"bits":5,"name": "imm[4:0]","type":4},{"bits":3,"name": 0x3,"type":2},{"bits":5,"name": "xs1","type":4},{"bits":5,"name": "xs2","type":4},{"bits":7,"name": "imm[11:5]","type":4}]}
 ....
 
 Description::
-Store 64 bits of data from register `xs2` to an
+For RV64, store 64 bits of data from register `xs2` to an
 address formed by adding `xs1` to a signed offset.
+<% if ext?(:Zilsd) %>
+For RV32, store doubleword from even/odd register pair.
+<% end %>
 
 
 Decode Variables::
+*RV32:*
+
 [width="100%", cols="1,2", options="header"]
 |===
 |Variable Name |Location
-|imm |sext({$encoding[31:25], $encoding[11:7]})
-|xs1 |$encoding[19:15]
+|imm |{$encoding[31:25], $encoding[11:7]}
 |xs2 |$encoding[24:20]
+|xs1 |$encoding[19:15]
 |===
 
-Included in::
-[options="autowrap,autowidth"]
-|===
-| Extension | Version
-
-| *I* | ~> 2.1.0
-
-|===
-
-
-[#udb:doc:inst:sd]
-== sd
-
-Synopsis::
-Store doubleword from even/odd register pair
-
-Assembly::
-sd xs2, offset(xs1)
-
-Encoding::
-[wavedrom, ,svg,subs='attributes',width="100%"]
-....
-{"reg":[{"bits":7,"name": 0x23,"type":2},{"bits":5,"name": "imm[4:0]","type":4},{"bits":3,"name": 0x3,"type":2},{"bits":5,"name": "xs1","type":4},{"bits":5,"name": "xs2 != {1,3,5,7,9,11,13,15,17,19,21,23,25,27,29,31}","type":4},{"bits":7,"name": "imm[11:5]","type":4}]}
-....
-
-Description::
-Stores a 64-bit value from registers xs2 and xs2+1. The effective address is obtained by adding
-register xs1 to the sign-extended 12-bit offset.
-
+*RV64:*
 
-Decode Variables::
 [width="100%", cols="1,2", options="header"]
 |===
 |Variable Name |Location
-|xs1 |$encoding[19:15]
+|imm |sext({$encoding[31:25], $encoding[11:7]})
 |xs2 |$encoding[24:20]
-|imm |{$encoding[31:25], $encoding[11:7]}
+|xs1 |$encoding[19:15]
 |===
 
 Included in::
 [options="autowrap,autowidth"]
 |===
 | Extension | Version
 
+| *I* | ~> 2.1.0
+
 | *Zilsd* | ~> 1.0
 
 |===

spec/std/isa/inst/I/ld.yaml

@@ -8,20 +8,37 @@ kind: instruction
 name: ld
 long_name: Load doubleword
 description: |
-  Load 64 bits of data into register `xd` from an
+  For RV64, load 64 bits of data into register `xd` from an
   address formed by adding `xs1` to a signed offset.
-definedBy: I
-base: 64
+  <% if ext?(:Zilsd) %>
+  For RV32, Loads a 64-bit value into registers xd and xd+1.
+  The effective address is obtained by adding
+  register xs1 to the sign-extended 12-bit offset.
+  <% end %>
+
+definedBy:
+  anyOf: [I, Zilsd]
 assembly: xd, imm(xs1)
 encoding:
-  match: -----------------011-----0000011
-  variables:
-    - name: imm
-      location: 31-20
-    - name: xs1
-      location: 19-15
-    - name: xd
-      location: 11-7
+  RV32:
+    match: -----------------011-----0000011
+    variables:
+      - name: imm
+        location: 31-20
+      - name: xs1
+        location: 19-15
+      - name: xd
+        location: 11-7
+        not: [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31]
+  RV64:
+    match: -----------------011-----0000011
+    variables:
+      - name: imm
+        location: 31-20
+      - name: xs1
+        location: 19-15
+      - name: xd
+        location: 11-7
 access:
   s: always
   u: always
@@ -30,7 +47,18 @@ access:
 operation(): |
   XReg virtual_address = X[xs1] + $signed(imm);
 
-  X[xd] = read_memory<64>(virtual_address, $encoding);
+  if (xlen() == 32) {
+    if (implemented?(ExtensionName::Zilsd)) {
+      Bits<64> data = read_memory<64>(virtual_address, $encoding);
+
+      X[xd] = data[31:0];
+      X[xd+1] = data[63:32];
+    } else {
+      raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+    }
+  } else {
+    X[xd] = read_memory<64>(virtual_address, $encoding);
+  }
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

spec/std/isa/inst/I/sd.yaml

@@ -8,30 +8,55 @@ kind: instruction
 name: sd
 long_name: Store doubleword
 description: |
-  Store 64 bits of data from register `xs2` to an
+  For RV64, store 64 bits of data from register `xs2` to an
   address formed by adding `xs1` to a signed offset.
-definedBy: I
-base: 64
+  <% if ext?(:Zilsd) %>
+  For RV32, store doubleword from even/odd register pair.
+  <% end %>
+definedBy:
+  anyOf: [I, Zilsd]
 assembly: xs2, imm(xs1)
 encoding:
-  match: -----------------011-----0100011
-  variables:
-    - name: imm
-      location: 31-25|11-7
-      sign_extend: true
-    - name: xs1
-      location: 19-15
-    - name: xs2
-      location: 24-20
+  RV32:
+    match: -----------------011-----0100011
+    variables:
+      - name: imm
+        location: 31-25|11-7
+      - name: xs2
+        not: [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31]
+        location: 24-20
+      - name: xs1
+        location: 19-15
+  RV64:
+    match: -----------------011-----0100011
+    variables:
+      - name: imm
+        location: 31-25|11-7
+        sign_extend: true
+      - name: xs2
+        location: 24-20
+      - name: xs1
+        location: 19-15
 access:
   s: always
   u: always
   vs: always
   vu: always
 operation(): |
+  Bits<64> data;
   XReg virtual_address = X[xs1] + $signed(imm);
 
-  write_memory<64>(virtual_address, X[xs2], $encoding);
+  if (xlen() == 32) {
+    if (implemented?(ExtensionName::Zclsd)) {
+      data = {X[xs2 + 1], X[xs2]};
+    } else {
+      raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
+    }
+  } else {
+    data = X[xs2];
+  }
+
+  write_memory<64>(virtual_address, data, $encoding);
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>