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fix(data): fix field names to be closer to operands (riscv-software-src#872)
- `dret`, `mnret`, and `sctrclr` take no operands. - ~~`sspush` and `sspopchk` are each single mnemonics that take a very restricted set of operand values. Also include a bit of documentation.~~ - `vaeskf1.vi`, `vaeskf2.vi`, `vsm3c.vi`, `vsm4k.vi`, `vwsll.vi`: renamed field to match operand.
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9 files changed

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‎backends/instructions_appendix/all_instructions.golden.adoc‎

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= Instruction Appendix
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:doctype: book
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:wavedrom: /workspaces/riscv-unified-db/node_modules/.bin/wavedrom-cli
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:wavedrom: /workspace/riscv-unified-db/node_modules/.bin/wavedrom-cli
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// Now the document header is complete and the wavedrom attribute is active.
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@@ -7146,9 +7146,6 @@ Included in::
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Synopsis::
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No synopsis available
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Assembly::
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dret dret
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Encoding::
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[wavedrom, ,svg,subs='attributes',width="100%"]
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....
@@ -15762,9 +15759,6 @@ Included in::
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Synopsis::
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Machine mode resume from the RNMI or Double Trap handler
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Assembly::
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mnret mnret
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Encoding::
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[wavedrom, ,svg,subs='attributes',width="100%"]
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Synopsis::
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No synopsis available
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Assembly::
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sctrclr sctrclr
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Encoding::
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[wavedrom, ,svg,subs='attributes',width="100%"]
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@@ -20761,7 +20752,7 @@ vaeskf1.vi vd, vs2, imm
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Encoding::
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[wavedrom, ,svg,subs='attributes',width="100%"]
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....
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{"reg":[{"bits":7,"name": 0x77,"type":2},{"bits":5,"name": "vd","type":4},{"bits":3,"name": 0x2,"type":2},{"bits":5,"name": "zimm5","type":4},{"bits":5,"name": "vs2","type":4},{"bits":7,"name": 0x45,"type":2}]}
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{"reg":[{"bits":7,"name": 0x77,"type":2},{"bits":5,"name": "vd","type":4},{"bits":3,"name": 0x2,"type":2},{"bits":5,"name": "imm","type":4},{"bits":5,"name": "vs2","type":4},{"bits":7,"name": 0x45,"type":2}]}
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Description::
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|===
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|Variable Name |Location
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|vs2 |$encoding[24:20]
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|zimm5 |$encoding[19:15]
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|imm |$encoding[19:15]
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|vd |$encoding[11:7]
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|===
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@@ -20799,7 +20790,7 @@ vaeskf2.vi vd, vs2, imm
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Encoding::
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[wavedrom, ,svg,subs='attributes',width="100%"]
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....
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{"reg":[{"bits":7,"name": 0x77,"type":2},{"bits":5,"name": "vd","type":4},{"bits":3,"name": 0x2,"type":2},{"bits":5,"name": "zimm5","type":4},{"bits":5,"name": "vs2","type":4},{"bits":7,"name": 0x55,"type":2}]}
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{"reg":[{"bits":7,"name": 0x77,"type":2},{"bits":5,"name": "vd","type":4},{"bits":3,"name": 0x2,"type":2},{"bits":5,"name": "imm","type":4},{"bits":5,"name": "vs2","type":4},{"bits":7,"name": 0x55,"type":2}]}
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Description::
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|===
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|Variable Name |Location
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|vs2 |$encoding[24:20]
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|zimm5 |$encoding[19:15]
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|imm |$encoding[19:15]
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|vd |$encoding[11:7]
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|===
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@@ -38678,7 +38669,7 @@ vsm3c.vi vd, vs2, imm
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Encoding::
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[wavedrom, ,svg,subs='attributes',width="100%"]
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....
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{"reg":[{"bits":7,"name": 0x77,"type":2},{"bits":5,"name": "vd","type":4},{"bits":3,"name": 0x2,"type":2},{"bits":5,"name": "zimm5","type":4},{"bits":5,"name": "vs2","type":4},{"bits":7,"name": 0x57,"type":2}]}
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{"reg":[{"bits":7,"name": 0x77,"type":2},{"bits":5,"name": "vd","type":4},{"bits":3,"name": 0x2,"type":2},{"bits":5,"name": "imm","type":4},{"bits":5,"name": "vs2","type":4},{"bits":7,"name": 0x57,"type":2}]}
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Description::
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|===
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|Variable Name |Location
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|vs2 |$encoding[24:20]
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|zimm5 |$encoding[19:15]
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|imm |$encoding[19:15]
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|vd |$encoding[11:7]
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|===
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@@ -38758,7 +38749,7 @@ vsm4k.vi vd, vs2, imm
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Encoding::
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[wavedrom, ,svg,subs='attributes',width="100%"]
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{"reg":[{"bits":7,"name": 0x77,"type":2},{"bits":5,"name": "vd","type":4},{"bits":3,"name": 0x2,"type":2},{"bits":5,"name": "zimm5","type":4},{"bits":5,"name": "vs2","type":4},{"bits":7,"name": 0x43,"type":2}]}
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{"reg":[{"bits":7,"name": 0x77,"type":2},{"bits":5,"name": "vd","type":4},{"bits":3,"name": 0x2,"type":2},{"bits":5,"name": "imm","type":4},{"bits":5,"name": "vs2","type":4},{"bits":7,"name": 0x43,"type":2}]}
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|===
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|Variable Name |Location
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|vs2 |$encoding[24:20]
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|zimm5 |$encoding[19:15]
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|imm |$encoding[19:15]
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|vd |$encoding[11:7]
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|===
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@@ -45361,7 +45352,7 @@ vwsll.vi vd, vs2, imm, vm
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Encoding::
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[wavedrom, ,svg,subs='attributes',width="100%"]
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{"reg":[{"bits":7,"name": 0x57,"type":2},{"bits":5,"name": "vd","type":4},{"bits":3,"name": 0x3,"type":2},{"bits":5,"name": "zimm5","type":4},{"bits":5,"name": "vs2","type":4},{"bits":1,"name": "vm","type":4},{"bits":6,"name": 0x35,"type":2}]}
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{"reg":[{"bits":7,"name": 0x57,"type":2},{"bits":5,"name": "vd","type":4},{"bits":3,"name": 0x3,"type":2},{"bits":5,"name": "imm","type":4},{"bits":5,"name": "vs2","type":4},{"bits":1,"name": "vm","type":4},{"bits":6,"name": 0x35,"type":2}]}
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|Variable Name |Location
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|vm |$encoding[25]
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|vs2 |$encoding[24:20]
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|zimm5 |$encoding[19:15]
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|imm |$encoding[19:15]
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|vd |$encoding[11:7]
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|===
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‎spec/std/isa/inst/Sdext/dret.yaml‎

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description: |
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No description available.
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definedBy: Sdext
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assembly: dret
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assembly: ""
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encoding:
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match: "01111011001000000000000001110011"
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variables: []

‎spec/std/isa/inst/Smdbltrp/sctrclr.yaml‎

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description: |
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No description available.
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assembly: sctrclr
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assembly: ""
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encoding:
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match: "00010000010000000000000001110011"
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variables: []

‎spec/std/isa/inst/Smrnmi/mnret.yaml‎

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also sets mstatus.MPRV to 0. If the Zicfilp extension is implemented, then if the new privileged mode is
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y, MNRET sets ELP to the logical AND of yLPE (see Section 22.1.1) and mnstatus.MNPELP.
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assembly: mnret
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assembly: ""
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variables: []

‎spec/std/isa/inst/Zvbb/vwsll.vi.yaml‎

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location: 25-25
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- name: vs2
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location: 24-20
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- name: zimm5
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- name: imm
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location: 19-15
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- name: vd
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location: 11-7

‎spec/std/isa/inst/Zvkned/vaeskf1.vi.yaml‎

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variables:
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- name: vs2
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- name: zimm5
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- name: imm
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location: 19-15
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- name: vd
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location: 11-7

‎spec/std/isa/inst/Zvkned/vaeskf2.vi.yaml‎

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variables:
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- name: imm
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- name: vd
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‎spec/std/isa/inst/Zvks/vsm3c.vi.yaml‎

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variables:
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- name: vs2
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- name: imm
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- name: vd
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‎spec/std/isa/inst/Zvks/vsm4k.vi.yaml‎

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variables:
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- name: zimm5
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- name: imm
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location: 19-15
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- name: vd
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location: 11-7

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