fix(data): rename operands to match Sail (riscv-software-src#859)

Author: ThinkOpenly

backends/instructions_appendix/all_instructions.golden.adoc

@@ -1,6 +1,6 @@
 = Instruction Appendix
 :doctype: book
-:wavedrom: /home/uniqueusman/riscv-unified-db/node_modules/.bin/wavedrom-cli
+:wavedrom: /workspace/riscv-unified-db/node_modules/.bin/wavedrom-cli
 // Now the document header is complete and the wavedrom attribute is active.
 
 
@@ -6155,13 +6155,13 @@ Atomic Read and Clear Bits in CSR with Immediate
 Encoding::
 [wavedrom, ,svg,subs='attributes',width="100%"]
 ....
-{"reg":[{"bits":7,"name": 0x73,"type":2},{"bits":5,"name": "xd","type":4},{"bits":3,"name": 0x7,"type":2},{"bits":5,"name": "uimm","type":4},{"bits":12,"name": "csr","type":4}]}
+{"reg":[{"bits":7,"name": 0x73,"type":2},{"bits":5,"name": "xd","type":4},{"bits":3,"name": 0x7,"type":2},{"bits":5,"name": "imm","type":4},{"bits":12,"name": "csr","type":4}]}
 ....
 
 Description::
 The CSRRCI variant is similar to CSRRC, except this updates the CSR using an XLEN-bit value obtained
-by zero-extending a 5-bit unsigned immediate (uimm[4:0]) field encoded in the `xs1` field instead of a
-value from an integer register. For CSRRCI, if the `uimm[4:0]` field is zero, then this instruction
+by zero-extending a 5-bit unsigned immediate (imm[4:0]) field encoded in the `xs1` field instead of a
+value from an integer register. For CSRRCI, if the `imm[4:0]` field is zero, then this instruction
 will not write to the CSR, and shall not cause any of the side effects that might otherwise occur on
 a CSR write, nor raise illegal-instruction exceptions on accesses to read-only CSRs. The CSRRCI will
 always read the CSR and cause any read side effects regardless of `xd` and `xs1` fields.
@@ -6172,7 +6172,7 @@ Decode Variables::
 |===
 |Variable Name |Location
 |csr |$encoding[31:20]
-|uimm |$encoding[19:15]
+|imm |$encoding[19:15]
 |xd |$encoding[11:7]
 |===
 
@@ -6237,13 +6237,13 @@ Atomic Read and Set Bits in CSR with Immediate
 Encoding::
 [wavedrom, ,svg,subs='attributes',width="100%"]
 ....
-{"reg":[{"bits":7,"name": 0x73,"type":2},{"bits":5,"name": "xd","type":4},{"bits":3,"name": 0x6,"type":2},{"bits":5,"name": "uimm","type":4},{"bits":12,"name": "csr","type":4}]}
+{"reg":[{"bits":7,"name": 0x73,"type":2},{"bits":5,"name": "xd","type":4},{"bits":3,"name": 0x6,"type":2},{"bits":5,"name": "imm","type":4},{"bits":12,"name": "csr","type":4}]}
 ....
 
 Description::
 The CSRRSI variant is similar to CSRRS, except this updates the CSR using an XLEN-bit value obtained
-by zero-extending a 5-bit unsigned immediate (uimm[4:0]) field encoded in the `xs1` field instead of a
-value from an integer register. For CSRRSI, if the `uimm[4:0]` field is zero, then this instruction
+by zero-extending a 5-bit unsigned immediate (imm[4:0]) field encoded in the `xs1` field instead of a
+value from an integer register. For CSRRSI, if the `imm[4:0]` field is zero, then this instruction
 will not write to the CSR, and shall not cause any of the side effects that might otherwise occur on
 a CSR write, nor raise illegal-instruction exceptions on accesses to read-only CSRs. The CSRRSI will
 always read the CSR and cause any read side effects regardless of `xd` and `xs1` fields.
@@ -6254,7 +6254,7 @@ Decode Variables::
 |===
 |Variable Name |Location
 |csr |$encoding[31:20]
-|uimm |$encoding[19:15]
+|imm |$encoding[19:15]
 |xd |$encoding[11:7]
 |===
 
@@ -19941,7 +19941,7 @@ No synopsis available
 Encoding::
 [wavedrom, ,svg,subs='attributes',width="100%"]
 ....
-{"reg":[{"bits":7,"name": 0x57,"type":2},{"bits":5,"name": "vd","type":4},{"bits":8,"name": 0x82,"type":2},{"bits":5,"name": "vs2","type":4},{"bits":1,"name": "vm","type":4},{"bits":6,"name": 0x10,"type":2}]}
+{"reg":[{"bits":7,"name": 0x57,"type":2},{"bits":5,"name": "xd","type":4},{"bits":8,"name": 0x82,"type":2},{"bits":5,"name": "vs2","type":4},{"bits":1,"name": "vm","type":4},{"bits":6,"name": 0x10,"type":2}]}
 ....
 
 Description::
@@ -19954,7 +19954,7 @@ Decode Variables::
 |Variable Name |Location
 |vm |$encoding[25]
 |vs2 |$encoding[24:20]
-|vd |$encoding[11:7]
+|xd |$encoding[11:7]
 |===
 
 Included in::

spec/std/isa/inst/V/vcpop.m.yaml

@@ -10,15 +10,15 @@ long_name: No synopsis available
 description: |
   No description available.
 definedBy: V
-assembly: vd, vs2, vm
+assembly: xd, vs2, vm
 encoding:
   match: 010000------10000010-----1010111
   variables:
     - name: vm
       location: 25-25
     - name: vs2
       location: 24-20
-    - name: vd
+    - name: xd
       location: 11-7
 access:
   s: always

spec/std/isa/inst/Zcd/c.fld.yaml

@@ -18,7 +18,7 @@ definedBy:
         - C
         - D
     - Zcd
-assembly: xd, imm(xs1)
+assembly: fd, imm(xs1)
 encoding:
   match: 001-----------00
   variables:

spec/std/isa/inst/Zcd/c.fsd.yaml

@@ -18,7 +18,7 @@ definedBy:
         - C
         - D
     - Zcd
-assembly: xs2, imm(xs1)
+assembly: fs2, imm(xs1)
 encoding:
   match: 101-----------00
   variables:

spec/std/isa/inst/Zicsr/csrrci.yaml

@@ -9,19 +9,19 @@ name: csrrci
 long_name: Atomic Read and Clear Bits in CSR with Immediate
 description: |
   The CSRRCI variant is similar to CSRRC, except this updates the CSR using an XLEN-bit value obtained
-  by zero-extending a 5-bit unsigned immediate (uimm[4:0]) field encoded in the `xs1` field instead of a
-  value from an integer register. For CSRRCI, if the `uimm[4:0]` field is zero, then this instruction
+  by zero-extending a 5-bit unsigned immediate (imm[4:0]) field encoded in the `xs1` field instead of a
+  value from an integer register. For CSRRCI, if the `imm[4:0]` field is zero, then this instruction
   will not write to the CSR, and shall not cause any of the side effects that might otherwise occur on
   a CSR write, nor raise illegal-instruction exceptions on accesses to read-only CSRs. The CSRRCI will
   always read the CSR and cause any read side effects regardless of `xd` and `xs1` fields.
 definedBy: Zicsr
-assembly: xd, csr, uimm
+assembly: xd, csr, imm
 encoding:
   match: -----------------111-----1110011
   variables:
     - name: csr
       location: 31-20
-    - name: uimm
+    - name: imm
       location: 19-15
     - name: xd
       location: 11-7
@@ -33,9 +33,9 @@ access:
 data_independent_timing: false
 pseudoinstructions:
   - when: xd == 0
-    to: csrci csr,uimm
+    to: csrci csr,imm
 operation(): |
-  Boolean will_write = uimm != 0;
+  Boolean will_write = imm != 0;
 
   Csr csr_handle = direct_csr_lookup(csr);
 
@@ -53,7 +53,7 @@ operation(): |
   if (will_write) {
     # set bits using the mask
     # performing any WARL transformations first
-    XReg mask = uimm;
+    XReg mask = imm;
     csr_sw_write(csr_handle, initial_csr_value & ~mask);
   }
 

spec/std/isa/inst/Zicsr/csrrsi.yaml

@@ -9,19 +9,19 @@ name: csrrsi
 long_name: Atomic Read and Set Bits in CSR with Immediate
 description: |
   The CSRRSI variant is similar to CSRRS, except this updates the CSR using an XLEN-bit value obtained
-  by zero-extending a 5-bit unsigned immediate (uimm[4:0]) field encoded in the `xs1` field instead of a
-  value from an integer register. For CSRRSI, if the `uimm[4:0]` field is zero, then this instruction
+  by zero-extending a 5-bit unsigned immediate (imm[4:0]) field encoded in the `xs1` field instead of a
+  value from an integer register. For CSRRSI, if the `imm[4:0]` field is zero, then this instruction
   will not write to the CSR, and shall not cause any of the side effects that might otherwise occur on
   a CSR write, nor raise illegal-instruction exceptions on accesses to read-only CSRs. The CSRRSI will
   always read the CSR and cause any read side effects regardless of `xd` and `xs1` fields.
 definedBy: Zicsr
-assembly: xd, csr, uimm
+assembly: xd, csr, imm
 encoding:
   match: -----------------110-----1110011
   variables:
     - name: csr
       location: 31-20
-    - name: uimm
+    - name: imm
       location: 19-15
     - name: xd
       location: 11-7
@@ -33,9 +33,9 @@ access:
 data_independent_timing: false
 pseudoinstructions:
   - when: xd == 0
-    to: csrsi csr,uimm
+    to: csrsi csr,imm
 operation(): |
-  Boolean will_write = uimm != 0;
+  Boolean will_write = imm != 0;
 
   Csr csr_handle = direct_csr_lookup(csr);
 
@@ -53,7 +53,7 @@ operation(): |
   if (will_write) {
     # set bits using the mask
     # performing any WARL transformations first
-    XReg mask = uimm;
+    XReg mask = imm;
     csr_sw_write(csr_handle, initial_csr_value | mask);
   }