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1 | 1 | /* |
2 | 2 | SSD_13XX - A fast SPI driver for several Solomon Systech SSD13xx series driver |
3 | | - Version: 1.0r3, beta release |
| 3 | + Version: 1.0r3, beta release (K64/K66 testing) |
4 | 4 |
|
5 | 5 | https://github.com/sumotoy/SSD_13XX |
6 | 6 |
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@@ -236,7 +236,9 @@ class SSD_13XX : public Print { |
236 | 236 | volatile int16_t _width, _height, _cursorX, _cursorY; |
237 | 237 | volatile bool _filled; |
238 | 238 | volatile uint8_t _remapReg; |
239 | | - |
| 239 | + #if defined(__MK64FX512__) || defined(__MK66FX1M0__) |
| 240 | + uint8_t _useSPI; |
| 241 | + #endif |
240 | 242 | /* ======================================================================== |
241 | 243 | Low Level SPI Routines |
242 | 244 | ========================================================================*/ |
@@ -416,76 +418,210 @@ class SSD_13XX : public Print { |
416 | 418 | uint8_t pcs_data, pcs_command; |
417 | 419 | uint8_t _mosi, _sclk; |
418 | 420 | uint8_t _cs,_dc; |
419 | | - |
| 421 | + |
420 | 422 | void startTransaction(void) |
421 | 423 | __attribute__((always_inline)) { |
422 | | - SPI.beginTransaction(SSD_13XXSPI); |
| 424 | + #if defined(__MK20DX128__) || defined(__MK20DX256__) |
| 425 | + SPI.beginTransaction(SSD_13XXSPI); |
| 426 | + #else |
| 427 | + if (_useSPI == 0){ |
| 428 | + SPI.beginTransaction(SSD_13XXSPI); |
| 429 | + } else if (_useSPI == 1){ |
| 430 | + SPI1.beginTransaction(SSD_13XXSPI); |
| 431 | + digitalWriteFast(_cs,LOW); |
| 432 | + } |
| 433 | + #endif |
423 | 434 | } |
424 | 435 |
|
425 | 436 | void endTransaction(void) |
426 | 437 | __attribute__((always_inline)) { |
427 | | - SPI.endTransaction(); |
| 438 | + #if defined(__MK20DX128__) || defined(__MK20DX256__) |
| 439 | + SPI.endTransaction(); |
| 440 | + #else |
| 441 | + if (_useSPI == 0){ |
| 442 | + SPI.endTransaction(); |
| 443 | + } else if (_useSPI == 1){ |
| 444 | + SPI1.endTransaction(); |
| 445 | + } |
| 446 | + #endif |
| 447 | + } |
| 448 | + |
| 449 | + #if defined(__MK64FX512__) || defined(__MK66FX1M0__) |
| 450 | + void disableCS(void) |
| 451 | + __attribute__((always_inline)) { |
| 452 | + if (_useSPI > 0) digitalWriteFast(_cs,HIGH); |
428 | 453 | } |
| 454 | + #endif |
429 | 455 |
|
430 | 456 | //Here's Paul Stoffregen SPI FIFO magic in action... |
431 | 457 | void waitFifoNotFull(void) { |
432 | 458 | uint32_t sr; |
433 | 459 | uint32_t tmp __attribute__((unused)); |
| 460 | + #if defined(__MK20DX128__) || defined(__MK20DX256__) |
434 | 461 | do { |
435 | 462 | sr = KINETISK_SPI0.SR; |
436 | 463 | if (sr & 0xF0) tmp = KINETISK_SPI0.POPR; // drain RX FIFO |
437 | 464 | } while ((sr & (15 << 12)) > (3 << 12)); |
| 465 | + #else |
| 466 | + if (_useSPI == 0){ |
| 467 | + do { |
| 468 | + sr = KINETISK_SPI0.SR; |
| 469 | + if (sr & 0xF0) tmp = KINETISK_SPI0.POPR; // drain RX FIFO |
| 470 | + } while ((sr & (15 << 12)) > (3 << 12)); |
| 471 | + } else if (_useSPI == 1){ |
| 472 | + do { |
| 473 | + sr = KINETISK_SPI1.SR; |
| 474 | + if (sr & 0xF0) tmp = KINETISK_SPI1.POPR; // drain RX FIFO |
| 475 | + } while ((sr & (15 << 12)) > (0 << 12)); |
| 476 | + } |
| 477 | + #endif |
438 | 478 | } |
439 | 479 |
|
440 | 480 | void waitTransmitComplete(uint32_t mcr) __attribute__((always_inline)) { |
441 | 481 | uint32_t tmp __attribute__((unused)); |
442 | | - while (1) { |
443 | | - uint32_t sr = KINETISK_SPI0.SR; |
444 | | - if (sr & SPI_SR_EOQF) break; // wait for last transmit |
445 | | - if (sr & 0xF0) tmp = KINETISK_SPI0.POPR; |
446 | | - } |
447 | | - KINETISK_SPI0.SR = SPI_SR_EOQF; |
448 | | - SPI0_MCR = mcr; |
449 | | - while (KINETISK_SPI0.SR & 0xF0) {tmp = KINETISK_SPI0.POPR;} |
| 482 | + uint32_t sr = 0; |
| 483 | + #if defined(__MK20DX128__) || defined(__MK20DX256__) |
| 484 | + while (1) { |
| 485 | + sr = KINETISK_SPI0.SR; |
| 486 | + if (sr & SPI_SR_EOQF) break; // wait for last transmit |
| 487 | + if (sr & 0xF0) tmp = KINETISK_SPI0.POPR; |
| 488 | + } |
| 489 | + KINETISK_SPI0.SR = SPI_SR_EOQF; |
| 490 | + SPI0_MCR = mcr; |
| 491 | + while (KINETISK_SPI0.SR & 0xF0) {tmp = KINETISK_SPI0.POPR;} |
| 492 | + #else |
| 493 | + if (_useSPI == 0){ |
| 494 | + while (1) { |
| 495 | + sr = KINETISK_SPI0.SR; |
| 496 | + if (sr & SPI_SR_EOQF) break; // wait for last transmit |
| 497 | + if (sr & 0xF0) tmp = KINETISK_SPI0.POPR; |
| 498 | + } |
| 499 | + KINETISK_SPI0.SR = SPI_SR_EOQF; |
| 500 | + SPI0_MCR = mcr; |
| 501 | + while (KINETISK_SPI0.SR & 0xF0) {tmp = KINETISK_SPI0.POPR;} |
| 502 | + } else if (_useSPI == 1){ |
| 503 | + while (1) { |
| 504 | + sr = KINETISK_SPI1.SR; |
| 505 | + if (sr & SPI_SR_EOQF) break; // wait for last transmit |
| 506 | + if (sr & 0xF0) tmp = KINETISK_SPI1.POPR; |
| 507 | + } |
| 508 | + KINETISK_SPI1.SR = SPI_SR_EOQF; |
| 509 | + SPI1_MCR = mcr; |
| 510 | + while (KINETISK_SPI1.SR & 0xF0) {tmp = KINETISK_SPI1.POPR;} |
| 511 | + } |
| 512 | + #endif |
450 | 513 | } |
451 | 514 |
|
452 | 515 | void writecommand_cont(const uint8_t c) __attribute__((always_inline)) { |
453 | | - KINETISK_SPI0.PUSHR = c | (pcs_command << 16) | SPI_PUSHR_CTAS(0) | SPI_PUSHR_CONT; |
| 516 | + #if defined(__MK20DX128__) || defined(__MK20DX256__) |
| 517 | + KINETISK_SPI0.PUSHR = c | (pcs_command << 16) | SPI_PUSHR_CTAS(0) | SPI_PUSHR_CONT; |
| 518 | + #else |
| 519 | + if (_useSPI == 0){ |
| 520 | + KINETISK_SPI0.PUSHR = c | (pcs_command << 16) | SPI_PUSHR_CTAS(0) | SPI_PUSHR_CONT; |
| 521 | + } else if (_useSPI == 1){ |
| 522 | + KINETISK_SPI1.PUSHR = c | (pcs_command << 16) | SPI_PUSHR_CTAS(0) | SPI_PUSHR_CONT; |
| 523 | + } |
| 524 | + #endif |
454 | 525 | waitFifoNotFull(); |
455 | 526 | } |
456 | | - |
457 | | - void writecommand16_cont(uint16_t c) __attribute__((always_inline)) { |
458 | | - KINETISK_SPI0.PUSHR = c | (pcs_command << 16) | SPI_PUSHR_CTAS(1) | SPI_PUSHR_CONT; |
| 527 | + |
| 528 | + void writecommand16_cont(const uint8_t c) __attribute__((always_inline)) { |
| 529 | + #if defined(__MK20DX128__) || defined(__MK20DX256__) |
| 530 | + KINETISK_SPI0.PUSHR = c | (pcs_command << 16) | SPI_PUSHR_CTAS(1) | SPI_PUSHR_CONT; |
| 531 | + #else |
| 532 | + if (_useSPI == 0){ |
| 533 | + KINETISK_SPI0.PUSHR = c | (pcs_command << 16) | SPI_PUSHR_CTAS(1) | SPI_PUSHR_CONT; |
| 534 | + } else if (_useSPI == 1){ |
| 535 | + KINETISK_SPI1.PUSHR = c | (pcs_command << 16) | SPI_PUSHR_CTAS(1) | SPI_PUSHR_CONT; |
| 536 | + } |
| 537 | + #endif |
459 | 538 | waitFifoNotFull(); |
460 | 539 | } |
461 | 540 |
|
462 | 541 | void writedata8_cont(uint8_t d) __attribute__((always_inline)) { |
463 | | - KINETISK_SPI0.PUSHR = d | (pcs_data << 16) | SPI_PUSHR_CTAS(0) | SPI_PUSHR_CONT; |
| 542 | + #if defined(__MK20DX128__) || defined(__MK20DX256__) |
| 543 | + KINETISK_SPI0.PUSHR = d | (pcs_data << 16) | SPI_PUSHR_CTAS(0) | SPI_PUSHR_CONT; |
| 544 | + #else |
| 545 | + if (_useSPI == 0){ |
| 546 | + KINETISK_SPI0.PUSHR = d | (pcs_data << 16) | SPI_PUSHR_CTAS(0) | SPI_PUSHR_CONT; |
| 547 | + } else if (_useSPI == 1){ |
| 548 | + KINETISK_SPI1.PUSHR = d | (pcs_data << 16) | SPI_PUSHR_CTAS(0) | SPI_PUSHR_CONT; |
| 549 | + } |
| 550 | + #endif |
464 | 551 | waitFifoNotFull(); |
465 | 552 | } |
466 | 553 |
|
467 | 554 | void writedata16_cont(uint16_t d) __attribute__((always_inline)) { |
468 | | - KINETISK_SPI0.PUSHR = d | (pcs_data << 16) | SPI_PUSHR_CTAS(1) | SPI_PUSHR_CONT; |
| 555 | + #if defined(__MK20DX128__) || defined(__MK20DX256__) |
| 556 | + KINETISK_SPI0.PUSHR = d | (pcs_data << 16) | SPI_PUSHR_CTAS(1) | SPI_PUSHR_CONT; |
| 557 | + #else |
| 558 | + if (_useSPI == 0){ |
| 559 | + KINETISK_SPI0.PUSHR = d | (pcs_data << 16) | SPI_PUSHR_CTAS(1) | SPI_PUSHR_CONT; |
| 560 | + } else if (_useSPI == 1){ |
| 561 | + KINETISK_SPI1.PUSHR = d | (pcs_data << 16) | SPI_PUSHR_CTAS(1) | SPI_PUSHR_CONT; |
| 562 | + } |
| 563 | + #endif |
469 | 564 | waitFifoNotFull(); |
470 | 565 | } |
471 | 566 |
|
472 | 567 | void writecommand_last(const uint8_t c) __attribute__((always_inline)) { |
473 | | - uint32_t mcr = SPI0_MCR; |
474 | | - KINETISK_SPI0.PUSHR = c | (pcs_command << 16) | SPI_PUSHR_CTAS(0) | SPI_PUSHR_EOQ; |
| 568 | + uint32_t mcr = 0; |
| 569 | + #if defined(__MK20DX128__) || defined(__MK20DX256__) |
| 570 | + mcr = SPI0_MCR; |
| 571 | + KINETISK_SPI0.PUSHR = c | (pcs_command << 16) | SPI_PUSHR_CTAS(0) | SPI_PUSHR_EOQ; |
| 572 | + #else |
| 573 | + if (_useSPI == 0){ |
| 574 | + mcr = SPI0_MCR; |
| 575 | + KINETISK_SPI0.PUSHR = c | (pcs_command << 16) | SPI_PUSHR_CTAS(0) | SPI_PUSHR_EOQ; |
| 576 | + } else if (_useSPI == 1){ |
| 577 | + mcr = SPI1_MCR; |
| 578 | + KINETISK_SPI1.PUSHR = c | (pcs_command << 16) | SPI_PUSHR_CTAS(0) | SPI_PUSHR_EOQ; |
| 579 | + } |
| 580 | + #endif |
475 | 581 | waitTransmitComplete(mcr); |
| 582 | + #if defined(__MK64FX512__) || defined(__MK66FX1M0__) |
| 583 | + disableCS(); |
| 584 | + #endif |
476 | 585 | } |
477 | 586 |
|
478 | | - |
479 | 587 | void writedata8_last(uint8_t c) __attribute__((always_inline)) { |
480 | | - uint32_t mcr = SPI0_MCR; |
481 | | - KINETISK_SPI0.PUSHR = c | (pcs_data << 16) | SPI_PUSHR_CTAS(0) | SPI_PUSHR_EOQ; |
| 588 | + uint32_t mcr = 0; |
| 589 | + #if defined(__MK20DX128__) || defined(__MK20DX256__) |
| 590 | + mcr = SPI0_MCR; |
| 591 | + KINETISK_SPI0.PUSHR = c | (pcs_data << 16) | SPI_PUSHR_CTAS(0) | SPI_PUSHR_EOQ; |
| 592 | + #else |
| 593 | + if (_useSPI == 0){ |
| 594 | + mcr = SPI0_MCR; |
| 595 | + KINETISK_SPI0.PUSHR = c | (pcs_data << 16) | SPI_PUSHR_CTAS(0) | SPI_PUSHR_EOQ; |
| 596 | + } else if (_useSPI == 1){ |
| 597 | + mcr = SPI1_MCR; |
| 598 | + KINETISK_SPI1.PUSHR = c | (pcs_data << 16) | SPI_PUSHR_CTAS(0) | SPI_PUSHR_EOQ; |
| 599 | + } |
| 600 | + #endif |
482 | 601 | waitTransmitComplete(mcr); |
| 602 | + #if defined(__MK64FX512__) || defined(__MK66FX1M0__) |
| 603 | + disableCS(); |
| 604 | + #endif |
483 | 605 | } |
484 | 606 |
|
485 | 607 | void writedata16_last(uint16_t d) __attribute__((always_inline)) { |
486 | | - uint32_t mcr = SPI0_MCR; |
487 | | - KINETISK_SPI0.PUSHR = d | (pcs_data << 16) | SPI_PUSHR_CTAS(1) | SPI_PUSHR_EOQ; |
| 608 | + uint32_t mcr = 0; |
| 609 | + #if defined(__MK20DX128__) || defined(__MK20DX256__) |
| 610 | + mcr = SPI0_MCR; |
| 611 | + KINETISK_SPI0.PUSHR = d | (pcs_data << 16) | SPI_PUSHR_CTAS(1) | SPI_PUSHR_EOQ; |
| 612 | + #else |
| 613 | + if (_useSPI == 0){ |
| 614 | + mcr = SPI0_MCR; |
| 615 | + KINETISK_SPI0.PUSHR = d | (pcs_data << 16) | SPI_PUSHR_CTAS(1) | SPI_PUSHR_EOQ; |
| 616 | + } else if (_useSPI == 1){ |
| 617 | + mcr = SPI1_MCR; |
| 618 | + KINETISK_SPI1.PUSHR = d | (pcs_data << 16) | SPI_PUSHR_CTAS(1) | SPI_PUSHR_EOQ; |
| 619 | + } |
| 620 | + #endif |
488 | 621 | waitTransmitComplete(mcr); |
| 622 | + #if defined(__MK64FX512__) || defined(__MK66FX1M0__) |
| 623 | + disableCS(); |
| 624 | + #endif |
489 | 625 | } |
490 | 626 |
|
491 | 627 | /* ----------------- ARM (XTENSA ESP8266) ------------------------*/ |
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