Update bsp/renesas/re6e1-fpb/ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/armv8m_mpu.h

二进制数据转16进制

Co-authored-by: Copilot <[email protected]>

Author: super-gith

bsp/renesas/re6e1-fpb/ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/armv8m_mpu.h

@@ -59,32 +59,32 @@
 /** \brief Normal memory outer-cacheable and inner-cacheable attributes
 * WT = Write Through, WB = Write Back, TR = Transient, RA = Read-Allocate, WA = Write Allocate
 */
-#define MPU_ATTR_NORMAL_OUTER_NON_CACHEABLE (0b0100)
-#define MPU_ATTR_NORMAL_OUTER_WT_TR_RA      (0b0010)
-#define MPU_ATTR_NORMAL_OUTER_WT_TR_WA      (0b0001)
-#define MPU_ATTR_NORMAL_OUTER_WT_TR_RA_WA   (0b0011)
-#define MPU_ATTR_NORMAL_OUTER_WT_RA         (0b1010)
-#define MPU_ATTR_NORMAL_OUTER_WT_WA         (0b1001)
-#define MPU_ATTR_NORMAL_OUTER_WT_RA_WA      (0b1011)
-#define MPU_ATTR_NORMAL_OUTER_WB_TR_RA      (0b0101)
-#define MPU_ATTR_NORMAL_OUTER_WB_TR_WA      (0b0110)
-#define MPU_ATTR_NORMAL_OUTER_WB_TR_RA_WA   (0b0111)
-#define MPU_ATTR_NORMAL_OUTER_WB_RA         (0b1101)
-#define MPU_ATTR_NORMAL_OUTER_WB_WA         (0b1110)
-#define MPU_ATTR_NORMAL_OUTER_WB_RA_WA      (0b1111)
-#define MPU_ATTR_NORMAL_INNER_NON_CACHEABLE (0b0100)
-#define MPU_ATTR_NORMAL_INNER_WT_TR_RA      (0b0010)
-#define MPU_ATTR_NORMAL_INNER_WT_TR_WA      (0b0001)
-#define MPU_ATTR_NORMAL_INNER_WT_TR_RA_WA   (0b0011)
-#define MPU_ATTR_NORMAL_INNER_WT_RA         (0b1010)
-#define MPU_ATTR_NORMAL_INNER_WT_WA         (0b1001)
-#define MPU_ATTR_NORMAL_INNER_WT_RA_WA      (0b1011)
-#define MPU_ATTR_NORMAL_INNER_WB_TR_RA      (0b0101)
-#define MPU_ATTR_NORMAL_INNER_WB_TR_WA      (0b0110)
-#define MPU_ATTR_NORMAL_INNER_WB_TR_RA_WA   (0b0111)
-#define MPU_ATTR_NORMAL_INNER_WB_RA         (0b1101)
-#define MPU_ATTR_NORMAL_INNER_WB_WA         (0b1110)
-#define MPU_ATTR_NORMAL_INNER_WB_RA_WA      (0b1111)
+#define MPU_ATTR_NORMAL_OUTER_NON_CACHEABLE (0x4)
+#define MPU_ATTR_NORMAL_OUTER_WT_TR_RA      (0x2)
+#define MPU_ATTR_NORMAL_OUTER_WT_TR_WA      (0x1)
+#define MPU_ATTR_NORMAL_OUTER_WT_TR_RA_WA   (0x3)
+#define MPU_ATTR_NORMAL_OUTER_WT_RA         (0xA)
+#define MPU_ATTR_NORMAL_OUTER_WT_WA         (0x9)
+#define MPU_ATTR_NORMAL_OUTER_WT_RA_WA      (0xB)
+#define MPU_ATTR_NORMAL_OUTER_WB_TR_RA      (0x5)
+#define MPU_ATTR_NORMAL_OUTER_WB_TR_WA      (0x6)
+#define MPU_ATTR_NORMAL_OUTER_WB_TR_RA_WA   (0x7)
+#define MPU_ATTR_NORMAL_OUTER_WB_RA         (0xD)
+#define MPU_ATTR_NORMAL_OUTER_WB_WA         (0xE)
+#define MPU_ATTR_NORMAL_OUTER_WB_RA_WA      (0xF)
+#define MPU_ATTR_NORMAL_INNER_NON_CACHEABLE (0x4)
+#define MPU_ATTR_NORMAL_INNER_WT_TR_RA      (0x2)
+#define MPU_ATTR_NORMAL_INNER_WT_TR_WA      (0x1)
+#define MPU_ATTR_NORMAL_INNER_WT_TR_RA_WA   (0x3)
+#define MPU_ATTR_NORMAL_INNER_WT_RA         (0xA)
+#define MPU_ATTR_NORMAL_INNER_WT_WA         (0x9)
+#define MPU_ATTR_NORMAL_INNER_WT_RA_WA      (0xB)
+#define MPU_ATTR_NORMAL_INNER_WB_TR_RA      (0x5)
+#define MPU_ATTR_NORMAL_INNER_WB_TR_WA      (0x6)
+#define MPU_ATTR_NORMAL_INNER_WB_TR_RA_WA   (0x7)
+#define MPU_ATTR_NORMAL_INNER_WB_RA         (0xD)
+#define MPU_ATTR_NORMAL_INNER_WB_WA         (0xE)
+#define MPU_ATTR_NORMAL_INNER_WB_RA_WA      (0xF)
 
 /** \brief Memory Attribute
 * \param O Outer memory attributes