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[AArch64] Verify consecutive vector registers in tbl, tbx (llvm#120262)
Table lookup instructions expect the vectors that define the table itself to be consecutive (wraparound allowed). Relevant documentation: https://developer.arm.com/documentation/100069/0606/SIMD-Vector-Instructions/TBL--vector-
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‎llvm/lib/Target/AArch64/AArch64InstrFormats.td‎

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -8160,28 +8160,28 @@ multiclass SIMDTableLookup<bit op, string asm> {
81608160

81618161
def : SIMDTableLookupAlias<asm # ".8b",
81628162
!cast<Instruction>(NAME#"v8i8One"),
8163-
V64, VecListOne128>;
8163+
V64, VecListOneConsecutive128>;
81648164
def : SIMDTableLookupAlias<asm # ".8b",
81658165
!cast<Instruction>(NAME#"v8i8Two"),
8166-
V64, VecListTwo128>;
8166+
V64, VecListTwoConsecutive128>;
81678167
def : SIMDTableLookupAlias<asm # ".8b",
81688168
!cast<Instruction>(NAME#"v8i8Three"),
8169-
V64, VecListThree128>;
8169+
V64, VecListThreeConsecutive128>;
81708170
def : SIMDTableLookupAlias<asm # ".8b",
81718171
!cast<Instruction>(NAME#"v8i8Four"),
8172-
V64, VecListFour128>;
8172+
V64, VecListFourConsecutive128>;
81738173
def : SIMDTableLookupAlias<asm # ".16b",
81748174
!cast<Instruction>(NAME#"v16i8One"),
8175-
V128, VecListOne128>;
8175+
V128, VecListOneConsecutive128>;
81768176
def : SIMDTableLookupAlias<asm # ".16b",
81778177
!cast<Instruction>(NAME#"v16i8Two"),
8178-
V128, VecListTwo128>;
8178+
V128, VecListTwoConsecutive128>;
81798179
def : SIMDTableLookupAlias<asm # ".16b",
81808180
!cast<Instruction>(NAME#"v16i8Three"),
8181-
V128, VecListThree128>;
8181+
V128, VecListThreeConsecutive128>;
81828182
def : SIMDTableLookupAlias<asm # ".16b",
81838183
!cast<Instruction>(NAME#"v16i8Four"),
8184-
V128, VecListFour128>;
8184+
V128, VecListFourConsecutive128>;
81858185
}
81868186

81878187
multiclass SIMDTableLookupTied<bit op, string asm> {
@@ -8204,28 +8204,28 @@ multiclass SIMDTableLookupTied<bit op, string asm> {
82048204

82058205
def : SIMDTableLookupAlias<asm # ".8b",
82068206
!cast<Instruction>(NAME#"v8i8One"),
8207-
V64, VecListOne128>;
8207+
V64, VecListOneConsecutive128>;
82088208
def : SIMDTableLookupAlias<asm # ".8b",
82098209
!cast<Instruction>(NAME#"v8i8Two"),
8210-
V64, VecListTwo128>;
8210+
V64, VecListTwoConsecutive128>;
82118211
def : SIMDTableLookupAlias<asm # ".8b",
82128212
!cast<Instruction>(NAME#"v8i8Three"),
8213-
V64, VecListThree128>;
8213+
V64, VecListThreeConsecutive128>;
82148214
def : SIMDTableLookupAlias<asm # ".8b",
82158215
!cast<Instruction>(NAME#"v8i8Four"),
8216-
V64, VecListFour128>;
8216+
V64, VecListFourConsecutive128>;
82178217
def : SIMDTableLookupAlias<asm # ".16b",
82188218
!cast<Instruction>(NAME#"v16i8One"),
8219-
V128, VecListOne128>;
8219+
V128, VecListOneConsecutive128>;
82208220
def : SIMDTableLookupAlias<asm # ".16b",
82218221
!cast<Instruction>(NAME#"v16i8Two"),
8222-
V128, VecListTwo128>;
8222+
V128, VecListTwoConsecutive128>;
82238223
def : SIMDTableLookupAlias<asm # ".16b",
82248224
!cast<Instruction>(NAME#"v16i8Three"),
8225-
V128, VecListThree128>;
8225+
V128, VecListThreeConsecutive128>;
82268226
def : SIMDTableLookupAlias<asm # ".16b",
82278227
!cast<Instruction>(NAME#"v16i8Four"),
8228-
V128, VecListFour128>;
8228+
V128, VecListFourConsecutive128>;
82298229
}
82308230

82318231
//----------------------------------------------------------------------------

‎llvm/lib/Target/AArch64/AArch64RegisterInfo.td‎

Lines changed: 12 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -598,7 +598,7 @@ class TypedVecListRegOperand<RegisterClass Reg, int lanes, string eltsize>
598598
# eltsize # "'>">;
599599

600600
multiclass VectorList<int count, RegisterClass Reg64, RegisterClass Reg128> {
601-
// With implicit types (probably on instruction instead). E.g. { v0, v1 }
601+
// With implicit types (probably on instruction instead). E.g. { v0, v1 } or {v0, v2, v4}.
602602
def _64AsmOperand : AsmOperandClass {
603603
let Name = NAME # "64";
604604
let PredicateMethod = "isImplicitlyTypedVectorList<RegKind::NeonVector, " # count # ">";
@@ -619,6 +619,17 @@ multiclass VectorList<int count, RegisterClass Reg64, RegisterClass Reg128> {
619619
let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_128AsmOperand");
620620
}
621621

622+
// With implicit types (probably on instruction instead), consecutive registers. E.g. { v0, v1, v2 }
623+
def _Consecutive128AsmOperand : AsmOperandClass {
624+
let Name = NAME # "Consecutive128";
625+
let PredicateMethod = "isImplicitlyTypedVectorList<RegKind::NeonVector, " # count # ", true>";
626+
let RenderMethod = "addVectorListOperands<AArch64Operand::VecListIdx_QReg, " # count # ", true>";
627+
}
628+
629+
def "Consecutive128" : RegisterOperand<Reg128, "printImplicitlyTypedVectorList"> {
630+
let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_Consecutive128AsmOperand");
631+
}
632+
622633
// 64-bit register lists with explicit type.
623634

624635
// { v0.8b, v1.8b }

‎llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp‎

Lines changed: 7 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1418,11 +1418,12 @@ class AArch64Operand : public MCParsedAsmOperand {
14181418

14191419
/// Is this a vector list with the type implicit (presumably attached to the
14201420
/// instruction itself)?
1421-
template <RegKind VectorKind, unsigned NumRegs>
1421+
template <RegKind VectorKind, unsigned NumRegs, bool IsConsecutive = false>
14221422
bool isImplicitlyTypedVectorList() const {
14231423
return Kind == k_VectorList && VectorList.Count == NumRegs &&
14241424
VectorList.NumElements == 0 &&
1425-
VectorList.RegisterKind == VectorKind;
1425+
VectorList.RegisterKind == VectorKind &&
1426+
(!IsConsecutive || (VectorList.Stride == 1));
14261427
}
14271428

14281429
template <RegKind VectorKind, unsigned NumRegs, unsigned NumElements,
@@ -1836,9 +1837,12 @@ class AArch64Operand : public MCParsedAsmOperand {
18361837
VecListIdx_PReg = 3,
18371838
};
18381839

1839-
template <VecListIndexType RegTy, unsigned NumRegs>
1840+
template <VecListIndexType RegTy, unsigned NumRegs,
1841+
bool IsConsecutive = false>
18401842
void addVectorListOperands(MCInst &Inst, unsigned N) const {
18411843
assert(N == 1 && "Invalid number of operands!");
1844+
assert((!IsConsecutive || (getVectorListStride() == 1)) &&
1845+
"Expected consecutive registers");
18421846
static const unsigned FirstRegs[][5] = {
18431847
/* DReg */ { AArch64::Q0,
18441848
AArch64::D0, AArch64::D0_D1,

‎llvm/test/MC/AArch64/neon-diagnostics.s‎

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -6888,6 +6888,9 @@
68886888
tbl v0.8b, {v1.8b, v2.8b, v3.8b}, v2.8b
68896889
tbl v0.8b, {v1.8b, v2.8b, v3.8b, v4.8b}, v2.8b
68906890
tbl v0.8b, {v1.16b, v2.16b, v3.16b, v4.16b, v5.16b}, v2.8b
6891+
tbl v0.8b, {v2.16b, v4.16b, v6.16b, v8.16b}, v10.8b
6892+
tbl.8b v0, {v2, v4, v6, v8}, v10
6893+
tbl.16b v0, {v2, v4, v6, v8}, v10
68916894

68926895
// CHECK-ERROR: error: invalid operand for instruction
68936896
// CHECK-ERROR: tbl v0.8b, {v1.8b}, v2.8b
@@ -6904,12 +6907,24 @@
69046907
// CHECK-ERROR: error: invalid number of vectors
69056908
// CHECK-ERROR: tbl v0.8b, {v1.16b, v2.16b, v3.16b, v4.16b, v5.16b}, v2.8b
69066909
// CHECK-ERROR: ^
6910+
// CHECK-ERROR: error: invalid operand for instruction
6911+
// CHECK-ERROR: tbl v0.8b, {v2.16b, v4.16b, v6.16b, v8.16b}, v10.8b
6912+
// CHECK-ERROR: ^
6913+
// CHECK-ERROR: error: invalid operand for instruction
6914+
// CHECK-ERROR: tbl.8b v0, {v2, v4, v6, v8}, v10
6915+
// CHECK-ERROR: ^
6916+
// CHECK-ERROR: error: invalid operand for instruction
6917+
// CHECK-ERROR: tbl.16b v0, {v2, v4, v6, v8}, v10
6918+
// CHECK-ERROR: ^
69076919

69086920
tbx v0.8b, {v1.8b}, v2.8b
69096921
tbx v0.8b, {v1.8b, v2.8b}, v2.8b
69106922
tbx v0.8b, {v1.8b, v2.8b, v3.8b}, v2.8b
69116923
tbx v0.8b, {v1.8b, v2.8b, v3.8b, v4.8b}, v2.8b
69126924
tbx v0.8b, {v1.16b, v2.16b, v3.16b, v4.16b, v5.16b}, v2.8b
6925+
tbx v0.8b, {v2.16b, v4.16b, v6.16b, v8.16b}, v10.8b
6926+
tbx.8b v0, {v2, v4, v6, v8}, v10
6927+
tbx.16b v0, {v2, v4, v6, v8}, v10
69136928

69146929
// CHECK-ERROR: error: invalid operand for instruction
69156930
// CHECK-ERROR: tbx v0.8b, {v1.8b}, v2.8b
@@ -6926,6 +6941,15 @@
69266941
// CHECK-ERROR: error: invalid number of vectors
69276942
// CHECK-ERROR: tbx v0.8b, {v1.16b, v2.16b, v3.16b, v4.16b, v5.16b}, v2.8b
69286943
// CHECK-ERROR: ^
6944+
// CHECK-ERROR: error: invalid operand for instruction
6945+
// CHECK-ERROR: tbx v0.8b, {v2.16b, v4.16b, v6.16b, v8.16b}, v10.8b
6946+
// CHECK-ERROR: ^
6947+
// CHECK-ERROR: error: invalid operand for instruction
6948+
// CHECK-ERROR: tbx.8b v0, {v2, v4, v6, v8}, v10
6949+
// CHECK-ERROR: ^
6950+
// CHECK-ERROR: error: invalid operand for instruction
6951+
// CHECK-ERROR: tbx.16b v0, {v2, v4, v6, v8}, v10
6952+
// CHECK-ERROR: ^
69296953

69306954
//----------------------------------------------------------------------
69316955
// Scalar Floating-point Convert To Lower Precision Narrow, Rounding To

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