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‎llvm/lib/Target/SPIRV/CMakeLists.txt

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@@ -26,6 +26,7 @@ add_llvm_target(SPIRVCodeGen
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SPIRVGlobalRegistry.cpp
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SPIRVInstrInfo.cpp
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SPIRVInstructionSelector.cpp
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SPIRVLegalizeImplicitBinding.cpp
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SPIRVStripConvergentIntrinsics.cpp
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SPIRVLegalizePointerCast.cpp
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SPIRVMergeRegionExitTargets.cpp

‎llvm/lib/Target/SPIRV/SPIRV.h

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@@ -23,6 +23,7 @@ ModulePass *createSPIRVPrepareFunctionsPass(const SPIRVTargetMachine &TM);
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FunctionPass *createSPIRVStructurizerPass();
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FunctionPass *createSPIRVMergeRegionExitTargetsPass();
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FunctionPass *createSPIRVStripConvergenceIntrinsicsPass();
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ModulePass *createSPIRVLegalizeImplicitBindingPass();
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FunctionPass *createSPIRVLegalizePointerCastPass(SPIRVTargetMachine *TM);
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FunctionPass *createSPIRVRegularizerPass();
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FunctionPass *createSPIRVPreLegalizerCombiner();
@@ -49,6 +50,7 @@ void initializeSPIRVRegularizerPass(PassRegistry &);
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void initializeSPIRVMergeRegionExitTargetsPass(PassRegistry &);
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void initializeSPIRVPrepareFunctionsPass(PassRegistry &);
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void initializeSPIRVStripConvergentIntrinsicsPass(PassRegistry &);
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void initializeSPIRVLegalizeImplicitBindingPass(PassRegistry &);
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} // namespace llvm
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#endif // LLVM_LIB_TARGET_SPIRV_SPIRV_H

‎llvm/lib/Target/SPIRV/SPIRVLegalizeImplicitBinding.cpp

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//===- SPIRVLegalizeImplicitBinding.cpp - Legalize implicit bindings ----*- C++
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//-*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass legalizes the @llvm.spv.resource.handlefromimplicitbinding
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// intrinsic by replacing it with a call to
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// @llvm.spv.resource.handlefrombinding.
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//
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//===----------------------------------------------------------------------===//
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#include "SPIRV.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/IR/IRBuilder.h"
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#include "llvm/IR/InstVisitor.h"
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#include "llvm/IR/Intrinsics.h"
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#include "llvm/IR/IntrinsicsSPIRV.h"
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#include "llvm/IR/Module.h"
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#include "llvm/Pass.h"
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#include <algorithm>
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#include <vector>
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using namespace llvm;
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namespace {
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class SPIRVLegalizeImplicitBinding : public ModulePass {
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public:
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static char ID;
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SPIRVLegalizeImplicitBinding() : ModulePass(ID) {}
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bool runOnModule(Module &M) override;
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private:
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void collectBindingInfo(Module &M);
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uint32_t getAndReserveFirstUnusedBinding(uint32_t DescSet);
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void replaceImplicitBindingCalls(Module &M);
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// A map from descriptor set to a bit vector of used binding numbers.
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std::vector<BitVector> UsedBindings;
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// A list of all implicit binding calls, to be sorted by order ID.
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SmallVector<CallInst *, 16> ImplicitBindingCalls;
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};
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struct BindingInfoCollector : public InstVisitor<BindingInfoCollector> {
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std::vector<BitVector> &UsedBindings;
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SmallVector<CallInst *, 16> &ImplicitBindingCalls;
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BindingInfoCollector(std::vector<BitVector> &UsedBindings,
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SmallVector<CallInst *, 16> &ImplicitBindingCalls)
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: UsedBindings(UsedBindings), ImplicitBindingCalls(ImplicitBindingCalls) {
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}
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void visitCallInst(CallInst &CI) {
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if (CI.getIntrinsicID() == Intrinsic::spv_resource_handlefrombinding) {
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const uint32_t DescSet =
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cast<ConstantInt>(CI.getArgOperand(0))->getZExtValue();
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const uint32_t Binding =
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cast<ConstantInt>(CI.getArgOperand(1))->getZExtValue();
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if (UsedBindings.size() <= DescSet) {
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UsedBindings.resize(DescSet + 1);
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UsedBindings[DescSet].resize(64);
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}
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if (UsedBindings[DescSet].size() <= Binding) {
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UsedBindings[DescSet].resize(2 * Binding + 1);
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}
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UsedBindings[DescSet].set(Binding);
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} else if (CI.getIntrinsicID() ==
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Intrinsic::spv_resource_handlefromimplicitbinding) {
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ImplicitBindingCalls.push_back(&CI);
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}
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}
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};
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void SPIRVLegalizeImplicitBinding::collectBindingInfo(Module &M) {
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BindingInfoCollector InfoCollector(UsedBindings, ImplicitBindingCalls);
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InfoCollector.visit(M);
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// Sort the collected calls by their order ID.
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std::sort(
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ImplicitBindingCalls.begin(), ImplicitBindingCalls.end(),
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[](const CallInst *A, const CallInst *B) {
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const uint32_t OrderIdArgIdx = 0;
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const uint32_t OrderA =
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cast<ConstantInt>(A->getArgOperand(OrderIdArgIdx))->getZExtValue();
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const uint32_t OrderB =
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cast<ConstantInt>(B->getArgOperand(OrderIdArgIdx))->getZExtValue();
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return OrderA < OrderB;
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});
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}
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uint32_t SPIRVLegalizeImplicitBinding::getAndReserveFirstUnusedBinding(
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uint32_t DescSet) {
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if (UsedBindings.size() <= DescSet) {
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UsedBindings.resize(DescSet + 1);
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UsedBindings[DescSet].resize(64);
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}
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int NewBinding = UsedBindings[DescSet].find_first_unset();
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if (NewBinding == -1) {
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NewBinding = UsedBindings[DescSet].size();
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UsedBindings[DescSet].resize(2 * NewBinding + 1);
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}
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UsedBindings[DescSet].set(NewBinding);
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return NewBinding;
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}
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void SPIRVLegalizeImplicitBinding::replaceImplicitBindingCalls(Module &M) {
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for (CallInst *OldCI : ImplicitBindingCalls) {
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IRBuilder<> Builder(OldCI);
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const uint32_t DescSet =
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cast<ConstantInt>(OldCI->getArgOperand(1))->getZExtValue();
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const uint32_t NewBinding = getAndReserveFirstUnusedBinding(DescSet);
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SmallVector<Value *, 8> Args;
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Args.push_back(Builder.getInt32(DescSet));
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Args.push_back(Builder.getInt32(NewBinding));
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// Copy the remaining arguments from the old call.
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for (uint32_t i = 2; i < OldCI->arg_size(); ++i) {
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Args.push_back(OldCI->getArgOperand(i));
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}
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Function *NewFunc = Intrinsic::getOrInsertDeclaration(
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&M, Intrinsic::spv_resource_handlefrombinding, OldCI->getType());
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CallInst *NewCI = Builder.CreateCall(NewFunc, Args);
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NewCI->setCallingConv(OldCI->getCallingConv());
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OldCI->replaceAllUsesWith(NewCI);
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OldCI->eraseFromParent();
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}
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}
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bool SPIRVLegalizeImplicitBinding::runOnModule(Module &M) {
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collectBindingInfo(M);
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if (ImplicitBindingCalls.empty()) {
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return false;
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}
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replaceImplicitBindingCalls(M);
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return true;
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}
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} // namespace
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char SPIRVLegalizeImplicitBinding::ID = 0;
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INITIALIZE_PASS(SPIRVLegalizeImplicitBinding, "legalize-spirv-implicit-binding",
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"Legalize SPIR-V implicit bindings", false, false)
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ModulePass *llvm::createSPIRVLegalizeImplicitBindingPass() {
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return new SPIRVLegalizeImplicitBinding();
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}

‎llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp

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@@ -226,6 +226,7 @@ void SPIRVPassConfig::addIRPasses() {
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}
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void SPIRVPassConfig::addISelPrepare() {
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addPass(createSPIRVLegalizeImplicitBindingPass());
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addPass(createSPIRVEmitIntrinsicsPass(&getTM<SPIRVTargetMachine>()));
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if (TM.getSubtargetImpl()->isLogicalSPIRV())
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addPass(createSPIRVLegalizePointerCastPass(&getTM<SPIRVTargetMachine>()));

‎llvm/test/CodeGen/SPIRV/hlsl-resources/ImplicitBinding.ll

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; RUN: llc -O0 -verify-machineinstrs -mtriple=spirv1.6-vulkan1.3-library %s -o - | FileCheck %s
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; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv1.6-vulkan1.3-library %s -o - -filetype=obj | spirv-val --target-env vulkan1.3 %}
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@.str = private unnamed_addr constant [2 x i8] c"b\00", align 1
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@.str.2 = private unnamed_addr constant [2 x i8] c"c\00", align 1
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@.str.4 = private unnamed_addr constant [2 x i8] c"d\00", align 1
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@.str.6 = private unnamed_addr constant [2 x i8] c"e\00", align 1
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@.str.8 = private unnamed_addr constant [2 x i8] c"f\00", align 1
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@.str.10 = private unnamed_addr constant [2 x i8] c"g\00", align 1
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@.str.12 = private unnamed_addr constant [2 x i8] c"h\00", align 1
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@.str.14 = private unnamed_addr constant [2 x i8] c"i\00", align 1
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; CHECK-DAG: OpName [[b:%[0-9]+]] "b"
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; CHECK-DAG: OpName [[c:%[0-9]+]] "c"
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; CHECK-DAG: OpName [[d:%[0-9]+]] "d"
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; CHECK-DAG: OpName [[e:%[0-9]+]] "e"
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; CHECK-DAG: OpName [[f:%[0-9]+]] "f"
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; CHECK-DAG: OpName [[g:%[0-9]+]] "g"
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; CHECK-DAG: OpName [[h:%[0-9]+]] "h"
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; CHECK-DAG: OpName [[i:%[0-9]+]] "i"
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; CHECK-DAG: OpDecorate [[b]] DescriptorSet 0
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; CHECK-DAG: OpDecorate [[b]] Binding 1
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; CHECK-DAG: OpDecorate [[c]] DescriptorSet 0
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; CHECK-DAG: OpDecorate [[c]] Binding 0
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; CHECK-DAG: OpDecorate [[d]] DescriptorSet 0
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; CHECK-DAG: OpDecorate [[d]] Binding 3
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; CHECK-DAG: OpDecorate [[e]] DescriptorSet 0
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; CHECK-DAG: OpDecorate [[e]] Binding 2
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; CHECK-DAG: OpDecorate [[f]] DescriptorSet 10
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; CHECK-DAG: OpDecorate [[f]] Binding 1
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; CHECK-DAG: OpDecorate [[g]] DescriptorSet 10
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; CHECK-DAG: OpDecorate [[g]] Binding 0
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; CHECK-DAG: OpDecorate [[h]] DescriptorSet 10
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; CHECK-DAG: OpDecorate [[h]] Binding 3
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; CHECK-DAG: OpDecorate [[i]] DescriptorSet 10
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; CHECK-DAG: OpDecorate [[i]] Binding 2
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define void @main() local_unnamed_addr #0 {
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entry:
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%0 = tail call target("spirv.SignedImage", i32, 5, 2, 0, 0, 2, 0) @llvm.spv.resource.handlefromimplicitbinding.tspirv.SignedImage_i32_5_2_0_0_2_0t(i32 0, i32 0, i32 1, i32 0, i1 false, ptr nonnull @.str)
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%1 = tail call target("spirv.SignedImage", i32, 5, 2, 0, 0, 2, 0) @llvm.spv.resource.handlefrombinding.tspirv.SignedImage_i32_5_2_0_0_2_0t(i32 0, i32 0, i32 1, i32 0, i1 false, ptr nonnull @.str.2)
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%2 = tail call target("spirv.SignedImage", i32, 5, 2, 0, 0, 2, 0) @llvm.spv.resource.handlefromimplicitbinding.tspirv.SignedImage_i32_5_2_0_0_2_0t(i32 1, i32 0, i32 1, i32 0, i1 false, ptr nonnull @.str.4)
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%3 = tail call target("spirv.SignedImage", i32, 5, 2, 0, 0, 2, 0) @llvm.spv.resource.handlefrombinding.tspirv.SignedImage_i32_5_2_0_0_2_0t(i32 0, i32 2, i32 1, i32 0, i1 false, ptr nonnull @.str.6)
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%4 = tail call target("spirv.SignedImage", i32, 5, 2, 0, 0, 2, 0) @llvm.spv.resource.handlefrombinding.tspirv.SignedImage_i32_5_2_0_0_2_0t(i32 10, i32 1, i32 1, i32 0, i1 false, ptr nonnull @.str.8)
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%5 = tail call target("spirv.SignedImage", i32, 5, 2, 0, 0, 2, 0) @llvm.spv.resource.handlefromimplicitbinding.tspirv.SignedImage_i32_5_2_0_0_2_0t(i32 2, i32 10, i32 1, i32 0, i1 false, ptr nonnull @.str.10)
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%6 = tail call target("spirv.SignedImage", i32, 5, 2, 0, 0, 2, 0) @llvm.spv.resource.handlefromimplicitbinding.tspirv.SignedImage_i32_5_2_0_0_2_0t(i32 3, i32 10, i32 1, i32 0, i1 false, ptr nonnull @.str.12)
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%7 = tail call target("spirv.SignedImage", i32, 5, 2, 0, 0, 2, 0) @llvm.spv.resource.handlefrombinding.tspirv.SignedImage_i32_5_2_0_0_2_0t(i32 10, i32 2, i32 1, i32 0, i1 false, ptr nonnull @.str.14)
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%8 = tail call noundef align 4 dereferenceable(4) ptr addrspace(11) @llvm.spv.resource.getpointer.p11.tspirv.SignedImage_i32_5_2_0_0_2_0t(target("spirv.SignedImage", i32, 5, 2, 0, 0, 2, 0) %1, i32 0)
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%9 = load i32, ptr addrspace(11) %8, align 4
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%10 = tail call noundef align 4 dereferenceable(4) ptr addrspace(11) @llvm.spv.resource.getpointer.p11.tspirv.SignedImage_i32_5_2_0_0_2_0t(target("spirv.SignedImage", i32, 5, 2, 0, 0, 2, 0) %2, i32 0)
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%11 = load i32, ptr addrspace(11) %10, align 4
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%add.i = add nsw i32 %11, %9
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%12 = tail call noundef align 4 dereferenceable(4) ptr addrspace(11) @llvm.spv.resource.getpointer.p11.tspirv.SignedImage_i32_5_2_0_0_2_0t(target("spirv.SignedImage", i32, 5, 2, 0, 0, 2, 0) %3, i32 0)
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%13 = load i32, ptr addrspace(11) %12, align 4
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%add4.i = add nsw i32 %add.i, %13
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%14 = tail call noundef align 4 dereferenceable(4) ptr addrspace(11) @llvm.spv.resource.getpointer.p11.tspirv.SignedImage_i32_5_2_0_0_2_0t(target("spirv.SignedImage", i32, 5, 2, 0, 0, 2, 0) %4, i32 0)
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%15 = load i32, ptr addrspace(11) %14, align 4
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%add6.i = add nsw i32 %add4.i, %15
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%16 = tail call noundef align 4 dereferenceable(4) ptr addrspace(11) @llvm.spv.resource.getpointer.p11.tspirv.SignedImage_i32_5_2_0_0_2_0t(target("spirv.SignedImage", i32, 5, 2, 0, 0, 2, 0) %5, i32 0)
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%17 = load i32, ptr addrspace(11) %16, align 4
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%add8.i = add nsw i32 %add6.i, %17
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%18 = tail call noundef align 4 dereferenceable(4) ptr addrspace(11) @llvm.spv.resource.getpointer.p11.tspirv.SignedImage_i32_5_2_0_0_2_0t(target("spirv.SignedImage", i32, 5, 2, 0, 0, 2, 0) %6, i32 0)
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%19 = load i32, ptr addrspace(11) %18, align 4
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%add10.i = add nsw i32 %add8.i, %19
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%20 = tail call noundef align 4 dereferenceable(4) ptr addrspace(11) @llvm.spv.resource.getpointer.p11.tspirv.SignedImage_i32_5_2_0_0_2_0t(target("spirv.SignedImage", i32, 5, 2, 0, 0, 2, 0) %7, i32 0)
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%21 = load i32, ptr addrspace(11) %20, align 4
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%add12.i = add nsw i32 %add10.i, %21
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%22 = tail call noundef align 4 dereferenceable(4) ptr addrspace(11) @llvm.spv.resource.getpointer.p11.tspirv.SignedImage_i32_5_2_0_0_2_0t(target("spirv.SignedImage", i32, 5, 2, 0, 0, 2, 0) %0, i32 0)
70+
store i32 %add12.i, ptr addrspace(11) %22, align 4
71+
ret void
72+
}
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attributes #0 = { "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" }

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