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Merge commit '1abeeabd65e6' from llvm.org/release/21.x into stable/21.x
2 parents 5068417 + 1abeeab commit 2c0ddfc

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3 files changed

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‎llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -738,7 +738,8 @@ void RISCVFrameLowering::allocateStack(MachineBasicBlock &MBB,
738738
MachineFunction &MF, uint64_t Offset,
739739
uint64_t RealStackSize, bool EmitCFI,
740740
bool NeedProbe, uint64_t ProbeSize,
741-
bool DynAllocation) const {
741+
bool DynAllocation,
742+
MachineInstr::MIFlag Flag) const {
742743
DebugLoc DL;
743744
const RISCVRegisterInfo *RI = STI.getRegisterInfo();
744745
const RISCVInstrInfo *TII = STI.getInstrInfo();
@@ -748,7 +749,7 @@ void RISCVFrameLowering::allocateStack(MachineBasicBlock &MBB,
748749
// Simply allocate the stack if it's not big enough to require a probe.
749750
if (!NeedProbe || Offset <= ProbeSize) {
750751
RI->adjustReg(MBB, MBBI, DL, SPReg, SPReg, StackOffset::getFixed(-Offset),
751-
MachineInstr::FrameSetup, getStackAlign());
752+
Flag, getStackAlign());
752753

753754
if (EmitCFI)
754755
CFIBuilder.buildDefCFAOffset(RealStackSize);
@@ -759,7 +760,7 @@ void RISCVFrameLowering::allocateStack(MachineBasicBlock &MBB,
759760
.addReg(RISCV::X0)
760761
.addReg(SPReg)
761762
.addImm(0)
762-
.setMIFlags(MachineInstr::FrameSetup);
763+
.setMIFlags(Flag);
763764
}
764765

765766
return;
@@ -770,14 +771,13 @@ void RISCVFrameLowering::allocateStack(MachineBasicBlock &MBB,
770771
uint64_t CurrentOffset = 0;
771772
while (CurrentOffset + ProbeSize <= Offset) {
772773
RI->adjustReg(MBB, MBBI, DL, SPReg, SPReg,
773-
StackOffset::getFixed(-ProbeSize), MachineInstr::FrameSetup,
774-
getStackAlign());
774+
StackOffset::getFixed(-ProbeSize), Flag, getStackAlign());
775775
// s[d|w] zero, 0(sp)
776776
BuildMI(MBB, MBBI, DL, TII->get(IsRV64 ? RISCV::SD : RISCV::SW))
777777
.addReg(RISCV::X0)
778778
.addReg(SPReg)
779779
.addImm(0)
780-
.setMIFlags(MachineInstr::FrameSetup);
780+
.setMIFlags(Flag);
781781

782782
CurrentOffset += ProbeSize;
783783
if (EmitCFI)
@@ -787,8 +787,7 @@ void RISCVFrameLowering::allocateStack(MachineBasicBlock &MBB,
787787
uint64_t Residual = Offset - CurrentOffset;
788788
if (Residual) {
789789
RI->adjustReg(MBB, MBBI, DL, SPReg, SPReg,
790-
StackOffset::getFixed(-Residual), MachineInstr::FrameSetup,
791-
getStackAlign());
790+
StackOffset::getFixed(-Residual), Flag, getStackAlign());
792791
if (EmitCFI)
793792
CFIBuilder.buildDefCFAOffset(Offset);
794793

@@ -798,7 +797,7 @@ void RISCVFrameLowering::allocateStack(MachineBasicBlock &MBB,
798797
.addReg(RISCV::X0)
799798
.addReg(SPReg)
800799
.addImm(0)
801-
.setMIFlags(MachineInstr::FrameSetup);
800+
.setMIFlags(Flag);
802801
}
803802
}
804803

@@ -812,8 +811,7 @@ void RISCVFrameLowering::allocateStack(MachineBasicBlock &MBB,
812811
Register TargetReg = RISCV::X6;
813812
// SUB TargetReg, SP, RoundedSize
814813
RI->adjustReg(MBB, MBBI, DL, TargetReg, SPReg,
815-
StackOffset::getFixed(-RoundedSize), MachineInstr::FrameSetup,
816-
getStackAlign());
814+
StackOffset::getFixed(-RoundedSize), Flag, getStackAlign());
817815

818816
if (EmitCFI) {
819817
// Set the CFA register to TargetReg.
@@ -830,14 +828,14 @@ void RISCVFrameLowering::allocateStack(MachineBasicBlock &MBB,
830828

831829
if (Residual) {
832830
RI->adjustReg(MBB, MBBI, DL, SPReg, SPReg, StackOffset::getFixed(-Residual),
833-
MachineInstr::FrameSetup, getStackAlign());
831+
Flag, getStackAlign());
834832
if (DynAllocation) {
835833
// s[d|w] zero, 0(sp)
836834
BuildMI(MBB, MBBI, DL, TII->get(IsRV64 ? RISCV::SD : RISCV::SW))
837835
.addReg(RISCV::X0)
838836
.addReg(SPReg)
839837
.addImm(0)
840-
.setMIFlags(MachineInstr::FrameSetup);
838+
.setMIFlags(Flag);
841839
}
842840
}
843841

@@ -1034,7 +1032,8 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
10341032
MF.getInfo<RISCVMachineFunctionInfo>()->hasDynamicAllocation();
10351033
if (StackSize != 0)
10361034
allocateStack(MBB, MBBI, MF, StackSize, RealStackSize, /*EmitCFI=*/true,
1037-
NeedProbe, ProbeSize, DynAllocation);
1035+
NeedProbe, ProbeSize, DynAllocation,
1036+
MachineInstr::FrameSetup);
10381037

10391038
// Save SiFive CLIC CSRs into Stack
10401039
emitSiFiveCLICPreemptibleSaves(MF, MBB, MBBI, DL);
@@ -1082,7 +1081,7 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
10821081

10831082
allocateStack(MBB, MBBI, MF, SecondSPAdjustAmount,
10841083
getStackSizeWithRVVPadding(MF), !hasFP(MF), NeedProbe,
1085-
ProbeSize, DynAllocation);
1084+
ProbeSize, DynAllocation, MachineInstr::FrameSetup);
10861085
}
10871086

10881087
if (RVVStackSize) {
@@ -1814,7 +1813,8 @@ MachineBasicBlock::iterator RISCVFrameLowering::eliminateCallFramePseudoInstr(
18141813
bool DynAllocation =
18151814
MF.getInfo<RISCVMachineFunctionInfo>()->hasDynamicAllocation();
18161815
allocateStack(MBB, MI, MF, -Amount, -Amount, !hasFP(MF),
1817-
/*NeedProbe=*/true, ProbeSize, DynAllocation);
1816+
/*NeedProbe=*/true, ProbeSize, DynAllocation,
1817+
MachineInstr::NoFlags);
18181818
} else {
18191819
const RISCVRegisterInfo &RI = *STI.getRegisterInfo();
18201820
RI.adjustReg(MBB, MI, DL, SPReg, SPReg, StackOffset::getFixed(Amount),

‎llvm/lib/Target/RISCV/RISCVFrameLowering.h

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -81,7 +81,8 @@ class RISCVFrameLowering : public TargetFrameLowering {
8181
void allocateStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
8282
MachineFunction &MF, uint64_t Offset,
8383
uint64_t RealStackSize, bool EmitCFI, bool NeedProbe,
84-
uint64_t ProbeSize, bool DynAllocation) const;
84+
uint64_t ProbeSize, bool DynAllocation,
85+
MachineInstr::MIFlag Flag) const;
8586

8687
protected:
8788
const RISCVSubtarget &STI;

‎llvm/test/CodeGen/RISCV/stack-probing-frame-setup.mir

Lines changed: 198 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,198 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
2+
# RUN: llc -mtriple=riscv64 -x mir -run-pass=prologepilog -verify-machineinstrs < %s \
3+
# RUN: | FileCheck %s -check-prefixes=RV64I
4+
# RUN: llc -mtriple=riscv32 -x mir -run-pass=prologepilog -verify-machineinstrs < %s \
5+
# RUN: | FileCheck %s -check-prefixes=RV32I
6+
--- |
7+
; Function Attrs: uwtable
8+
define void @no_reserved_call_frame(i64 %n) #0 {
9+
entry:
10+
%v = alloca i32, i64 %n, align 4
11+
call void @callee_stack_args(ptr %v, [518 x i64] poison)
12+
ret void
13+
}
14+
15+
declare void @callee_stack_args(ptr, [518 x i64]) #1
16+
17+
attributes #0 = { uwtable "frame-pointer"="none" "probe-stack"="inline-asm" "target-features"="+m" }
18+
attributes #1 = { "target-features"="+m" }
19+
...
20+
---
21+
name: no_reserved_call_frame
22+
alignment: 4
23+
exposesReturnsTwice: false
24+
legalized: false
25+
regBankSelected: false
26+
selected: false
27+
failedISel: false
28+
tracksRegLiveness: true
29+
hasWinCFI: false
30+
noPhis: true
31+
isSSA: false
32+
noVRegs: true
33+
hasFakeUses: false
34+
callsEHReturn: false
35+
callsUnwindInit: false
36+
hasEHContTarget: false
37+
hasEHScopes: false
38+
hasEHFunclets: false
39+
isOutlined: false
40+
debugInstrRef: false
41+
failsVerification: false
42+
tracksDebugUserValues: true
43+
registers: []
44+
liveins:
45+
- { reg: '$x10', virtual-reg: '' }
46+
frameInfo:
47+
isFrameAddressTaken: false
48+
isReturnAddressTaken: false
49+
hasStackMap: false
50+
hasPatchPoint: false
51+
stackSize: 0
52+
offsetAdjustment: 0
53+
maxAlignment: 8
54+
adjustsStack: true
55+
hasCalls: true
56+
stackProtector: ''
57+
functionContext: ''
58+
maxCallFrameSize: 4294967295
59+
cvBytesOfCalleeSavedRegisters: 0
60+
hasOpaqueSPAdjustment: false
61+
hasVAStart: false
62+
hasMustTailInVarArgFunc: false
63+
hasTailCall: false
64+
isCalleeSavedInfoValid: false
65+
localFrameSize: 0
66+
savePoint: ''
67+
restorePoint: ''
68+
fixedStack: []
69+
stack:
70+
- { id: 0, name: v, type: variable-sized, offset: 0, alignment: 1, stack-id: default,
71+
callee-saved-register: '', callee-saved-restored: true, local-offset: 0,
72+
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
73+
entry_values: []
74+
callSites: []
75+
debugValueSubstitutions: []
76+
constants: []
77+
machineFunctionInfo:
78+
varArgsFrameIndex: 0
79+
varArgsSaveSize: 0
80+
body: |
81+
; RV64I-LABEL: name: no_reserved_call_frame
82+
; RV64I: bb.0.entry:
83+
; RV64I-NEXT: successors: %bb.1(0x80000000)
84+
; RV64I-NEXT: liveins: $x10, $x1
85+
; RV64I-NEXT: {{ $}}
86+
; RV64I-NEXT: $x2 = frame-setup ADDI $x2, -16
87+
; RV64I-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16
88+
; RV64I-NEXT: frame-setup SD killed $x1, $x2, 8 :: (store (s64) into %stack.1)
89+
; RV64I-NEXT: frame-setup SD killed $x8, $x2, 0 :: (store (s64) into %stack.2)
90+
; RV64I-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -8
91+
; RV64I-NEXT: frame-setup CFI_INSTRUCTION offset $x8, -16
92+
; RV64I-NEXT: $x8 = frame-setup ADDI $x2, 16
93+
; RV64I-NEXT: frame-setup CFI_INSTRUCTION def_cfa $x8, 0
94+
; RV64I-NEXT: renamable $x10 = SLLI killed renamable $x10, 2
95+
; RV64I-NEXT: renamable $x10 = nuw ADDI killed renamable $x10, 15
96+
; RV64I-NEXT: renamable $x10 = ANDI killed renamable $x10, -16
97+
; RV64I-NEXT: renamable $x10 = SUB $x2, killed renamable $x10
98+
; RV64I-NEXT: renamable $x11 = LUI 1
99+
; RV64I-NEXT: {{ $}}
100+
; RV64I-NEXT: bb.1.entry:
101+
; RV64I-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
102+
; RV64I-NEXT: liveins: $x10, $x11
103+
; RV64I-NEXT: {{ $}}
104+
; RV64I-NEXT: $x2 = SUB $x2, renamable $x11
105+
; RV64I-NEXT: SD $x0, $x2, 0
106+
; RV64I-NEXT: BLT renamable $x10, $x2, %bb.1
107+
; RV64I-NEXT: {{ $}}
108+
; RV64I-NEXT: bb.2.entry:
109+
; RV64I-NEXT: liveins: $x10
110+
; RV64I-NEXT: {{ $}}
111+
; RV64I-NEXT: $x2 = ADDI renamable $x10, 0
112+
; RV64I-NEXT: $x11 = LUI 1
113+
; RV64I-NEXT: $x2 = SUB $x2, killed $x11
114+
; RV64I-NEXT: PseudoCALL target-flags(riscv-call) @callee_stack_args, csr_ilp32_lp64, implicit-def dead $x1, implicit $x10, implicit undef $x11, implicit undef $x12, implicit undef $x13, implicit undef $x14, implicit undef $x15, implicit undef $x16, implicit undef $x17, implicit-def $x2
115+
; RV64I-NEXT: $x10 = LUI 1
116+
; RV64I-NEXT: $x2 = ADD $x2, killed $x10
117+
; RV64I-NEXT: $x2 = frame-destroy ADDI $x8, -16
118+
; RV64I-NEXT: frame-destroy CFI_INSTRUCTION def_cfa $x2, 16
119+
; RV64I-NEXT: $x1 = frame-destroy LD $x2, 8 :: (load (s64) from %stack.1)
120+
; RV64I-NEXT: $x8 = frame-destroy LD $x2, 0 :: (load (s64) from %stack.2)
121+
; RV64I-NEXT: frame-destroy CFI_INSTRUCTION restore $x1
122+
; RV64I-NEXT: frame-destroy CFI_INSTRUCTION restore $x8
123+
; RV64I-NEXT: $x2 = frame-destroy ADDI $x2, 16
124+
; RV64I-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_offset 0
125+
; RV64I-NEXT: PseudoRET
126+
;
127+
; RV32I-LABEL: name: no_reserved_call_frame
128+
; RV32I: bb.0.entry:
129+
; RV32I-NEXT: successors: %bb.1(0x80000000)
130+
; RV32I-NEXT: liveins: $x10, $x1
131+
; RV32I-NEXT: {{ $}}
132+
; RV32I-NEXT: $x2 = frame-setup ADDI $x2, -16
133+
; RV32I-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16
134+
; RV32I-NEXT: frame-setup SW killed $x1, $x2, 12 :: (store (s32) into %stack.1)
135+
; RV32I-NEXT: frame-setup SW killed $x8, $x2, 8 :: (store (s32) into %stack.2)
136+
; RV32I-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -4
137+
; RV32I-NEXT: frame-setup CFI_INSTRUCTION offset $x8, -8
138+
; RV32I-NEXT: $x8 = frame-setup ADDI $x2, 16
139+
; RV32I-NEXT: frame-setup CFI_INSTRUCTION def_cfa $x8, 0
140+
; RV32I-NEXT: renamable $x10 = SLLI killed renamable $x10, 2
141+
; RV32I-NEXT: renamable $x10 = nuw ADDI killed renamable $x10, 15
142+
; RV32I-NEXT: renamable $x10 = ANDI killed renamable $x10, -16
143+
; RV32I-NEXT: renamable $x10 = SUB $x2, killed renamable $x10
144+
; RV32I-NEXT: renamable $x11 = LUI 1
145+
; RV32I-NEXT: {{ $}}
146+
; RV32I-NEXT: bb.1.entry:
147+
; RV32I-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
148+
; RV32I-NEXT: liveins: $x10, $x11
149+
; RV32I-NEXT: {{ $}}
150+
; RV32I-NEXT: $x2 = SUB $x2, renamable $x11
151+
; RV32I-NEXT: SD $x0, $x2, 0
152+
; RV32I-NEXT: BLT renamable $x10, $x2, %bb.1
153+
; RV32I-NEXT: {{ $}}
154+
; RV32I-NEXT: bb.2.entry:
155+
; RV32I-NEXT: liveins: $x10
156+
; RV32I-NEXT: {{ $}}
157+
; RV32I-NEXT: $x2 = ADDI renamable $x10, 0
158+
; RV32I-NEXT: $x11 = LUI 1
159+
; RV32I-NEXT: $x2 = SUB $x2, killed $x11
160+
; RV32I-NEXT: PseudoCALL target-flags(riscv-call) @callee_stack_args, csr_ilp32_lp64, implicit-def dead $x1, implicit $x10, implicit undef $x11, implicit undef $x12, implicit undef $x13, implicit undef $x14, implicit undef $x15, implicit undef $x16, implicit undef $x17, implicit-def $x2
161+
; RV32I-NEXT: $x10 = LUI 1
162+
; RV32I-NEXT: $x2 = ADD $x2, killed $x10
163+
; RV32I-NEXT: $x2 = frame-destroy ADDI $x8, -16
164+
; RV32I-NEXT: frame-destroy CFI_INSTRUCTION def_cfa $x2, 16
165+
; RV32I-NEXT: $x1 = frame-destroy LW $x2, 12 :: (load (s32) from %stack.1)
166+
; RV32I-NEXT: $x8 = frame-destroy LW $x2, 8 :: (load (s32) from %stack.2)
167+
; RV32I-NEXT: frame-destroy CFI_INSTRUCTION restore $x1
168+
; RV32I-NEXT: frame-destroy CFI_INSTRUCTION restore $x8
169+
; RV32I-NEXT: $x2 = frame-destroy ADDI $x2, 16
170+
; RV32I-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_offset 0
171+
; RV32I-NEXT: PseudoRET
172+
bb.0.entry:
173+
successors: %bb.1(0x80000000)
174+
liveins: $x10
175+
176+
renamable $x10 = SLLI killed renamable $x10, 2
177+
renamable $x10 = nuw ADDI killed renamable $x10, 15
178+
renamable $x10 = ANDI killed renamable $x10, -16
179+
renamable $x10 = SUB $x2, killed renamable $x10
180+
renamable $x11 = LUI 1
181+
182+
bb.1.entry:
183+
successors: %bb.2(0x40000000), %bb.1(0x40000000)
184+
liveins: $x10, $x11
185+
186+
$x2 = SUB $x2, renamable $x11
187+
SD $x0, $x2, 0
188+
BLT renamable $x10, $x2, %bb.1
189+
190+
bb.2.entry:
191+
liveins: $x10
192+
193+
$x2 = ADDI renamable $x10, 0
194+
ADJCALLSTACKDOWN 4088, 0, implicit-def dead $x2, implicit $x2
195+
PseudoCALL target-flags(riscv-call) @callee_stack_args, csr_ilp32_lp64, implicit-def dead $x1, implicit $x10, implicit undef $x11, implicit undef $x12, implicit undef $x13, implicit undef $x14, implicit undef $x15, implicit undef $x16, implicit undef $x17, implicit-def $x2
196+
ADJCALLSTACKUP 4088, 0, implicit-def dead $x2, implicit $x2
197+
PseudoRET
198+
...

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