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#define WCR_LOAD ((uint32_t )(1u << 3 ))
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#define WCR_STORE ((uint32_t )(1u << 4 ))
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- // Enable breakpoint, watchpoint, and vector catch debug exceptions.
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- // (MDE bit in the MDSCR_EL1 register. Equivalent to the MDBGen bit in
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- // DBGDSCRext in Aarch32)
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- #define MDE_ENABLE ((uint32_t )(1u << 15 ))
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-
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// Single instruction step
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// (SS bit in the MDSCR_EL1 register)
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#define SS_ENABLE ((uint32_t )(1u ))
@@ -804,8 +799,6 @@ uint32_t DNBArchMachARM64::EnableHardwareBreakpoint(nub_addr_t addr,
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(uint64_t )m_state.dbg .__bvr [i],
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(uint32_t )m_state.dbg .__bcr [i]);
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- // The kernel will set the MDE_ENABLE bit in the MDSCR_EL1 for us
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- // automatically, don't need to do it here.
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kret = SetDBGState (also_set_on_task);
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DNBLogThreadedIf (LOG_WATCHPOINTS,
@@ -845,9 +838,10 @@ DNBArchMachARM64::AlignRequestedWatchpoint(nub_addr_t requested_addr,
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// / Round up \a requested_size to the next power-of-2 size, at least 8
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// / bytes
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- // / requested_size == 3 -> aligned_size == 8
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- // / requested_size == 13 -> aligned_size == 16
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- // / requested_size == 16 -> aligned_size == 16
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+ // / requested_size == 8 -> aligned_size == 8
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+ // / requested_size == 9 -> aligned_size == 16
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+ // / requested_size == 15 -> aligned_size == 16
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+ // / requested_size == 192 -> aligned_size == 256
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// / Could be `std::bit_ceil(aligned_size)` when we build with C++20?
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aligned_size = 1ULL << (addr_bit_size - __builtin_clzll (aligned_size - 1 ));
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@@ -919,7 +913,7 @@ uint32_t DNBArchMachARM64::EnableHardwareWatchpoint(nub_addr_t addr,
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if (wps[0 ].aligned_size <= 8 )
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return SetBASWatchpoint (wps[0 ], read, write, also_set_on_task);
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else
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- return INVALID_NUB_HW_INDEX ;
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+ return SetMASKWatchpoint (wps[ 0 ], read, write, also_set_on_task) ;
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}
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// We have multiple WatchpointSpecs
@@ -1021,9 +1015,6 @@ uint32_t DNBArchMachARM64::SetBASWatchpoint(DNBArchMachARM64::WatchpointSpec wp,
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(uint64_t )m_state.dbg .__wvr [i],
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(uint32_t )m_state.dbg .__wcr [i]);
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- // The kernel will set the MDE_ENABLE bit in the MDSCR_EL1 for us
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- // automatically, don't need to do it here.
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-
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kret = SetDBGState (also_set_on_task);
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// DumpDBGState(m_state.dbg);
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@@ -1039,6 +1030,81 @@ uint32_t DNBArchMachARM64::SetBASWatchpoint(DNBArchMachARM64::WatchpointSpec wp,
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return INVALID_NUB_HW_INDEX;
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}
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+ uint32_t
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+ DNBArchMachARM64::SetMASKWatchpoint (DNBArchMachARM64::WatchpointSpec wp,
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+ bool read, bool write,
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+ bool also_set_on_task) {
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+ const uint32_t num_hw_watchpoints = NumSupportedHardwareWatchpoints ();
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+
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+ // Read the debug state
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+ kern_return_t kret = GetDBGState (false );
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+ if (kret != KERN_SUCCESS)
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+ return INVALID_NUB_HW_INDEX;
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+
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+ // Check to make sure we have the needed hardware support
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+ uint32_t i = 0 ;
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+
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+ for (i = 0 ; i < num_hw_watchpoints; ++i) {
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+ if ((m_state.dbg .__wcr [i] & WCR_ENABLE) == 0 )
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+ break ; // We found an available hw watchpoint slot
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+ }
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+ if (i == num_hw_watchpoints) {
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+ DNBLogThreadedIf (LOG_WATCHPOINTS,
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+ " DNBArchMachARM64::"
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+ " SetMASKWatchpoint(): All "
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+ " hardware resources (%u) are in use." ,
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+ num_hw_watchpoints);
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+ return INVALID_NUB_HW_INDEX;
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+ }
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+
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+ DNBLogThreadedIf (LOG_WATCHPOINTS,
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+ " DNBArchMachARM64::"
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+ " SetMASKWatchpoint() "
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+ " set hardware register %d to MASK watchpoint "
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+ " aligned start address 0x%llx, aligned size %zu" ,
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+ i, wp.aligned_start , wp.aligned_size );
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+
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+ // Clear any previous LoHi joined-watchpoint that may have been in use
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+ LoHi[i] = 0 ;
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+
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+ // MASK field is the number of low bits that are masked off
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+ // when comparing the address with the DBGWVR<n>_EL1 values.
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+ // If aligned size is 16, that means we ignore low 4 bits, 0b1111.
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+ // popcount(16 - 1) give us the correct value of 4.
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+ // 2GB is max watchable region, which is 31 bits (low bits 0x7fffffff
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+ // masked off) -- a MASK value of 31.
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+ const uint64_t mask = __builtin_popcountl (wp.aligned_size - 1 ) << 24 ;
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+ // A '0b11111111' BAS value needed for mask watchpoints plus a
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+ // nonzero mask value.
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+ const uint64_t not_bas_wp = 0xff << 5 ;
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+
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+ m_state.dbg .__wvr [i] = wp.aligned_start ;
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+ m_state.dbg .__wcr [i] = mask | not_bas_wp | S_USER | // Stop only in user mode
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+ (read ? WCR_LOAD : 0 ) | // Stop on read access?
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+ (write ? WCR_STORE : 0 ) | // Stop on write access?
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+ WCR_ENABLE; // Enable this watchpoint;
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+
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+ DNBLogThreadedIf (LOG_WATCHPOINTS,
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+ " DNBArchMachARM64::SetMASKWatchpoint() "
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+ " adding watchpoint on address 0x%llx with control "
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+ " register value 0x%llx" ,
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+ (uint64_t )m_state.dbg .__wvr [i],
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+ (uint64_t )m_state.dbg .__wcr [i]);
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+
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+ kret = SetDBGState (also_set_on_task);
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+
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+ DNBLogThreadedIf (LOG_WATCHPOINTS,
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+ " DNBArchMachARM64::"
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+ " SetMASKWatchpoint() "
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+ " SetDBGState() => 0x%8.8x." ,
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+ kret);
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+
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+ if (kret == KERN_SUCCESS)
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+ return i;
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+
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+ return INVALID_NUB_HW_INDEX;
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+ }
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+
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bool DNBArchMachARM64::ReenableHardwareWatchpoint (uint32_t hw_index) {
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// If this logical watchpoint # is actually implemented using
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// two hardware watchpoint registers, re-enable both of them.
@@ -1065,14 +1131,11 @@ bool DNBArchMachARM64::ReenableHardwareWatchpoint_helper(uint32_t hw_index) {
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DNBLogThreadedIf (LOG_WATCHPOINTS,
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" DNBArchMachARM64::"
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- " SetBASWatchpoint ( %u ) - WVR%u = "
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+ " ReenableHardwareWatchpoint_helper ( %u ) - WVR%u = "
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" 0x%8.8llx WCR%u = 0x%8.8llx" ,
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hw_index, hw_index, (uint64_t )m_state.dbg .__wvr [hw_index],
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hw_index, (uint64_t )m_state.dbg .__wcr [hw_index]);
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- // The kernel will set the MDE_ENABLE bit in the MDSCR_EL1 for us
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- // automatically, don't need to do it here.
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-
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kret = SetDBGState (false );
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return (kret == KERN_SUCCESS);
@@ -1174,30 +1237,60 @@ uint32_t DNBArchMachARM64::GetHardwareWatchpointHit(nub_addr_t &addr) {
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uint32_t i, num = NumSupportedHardwareWatchpoints ();
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for (i = 0 ; i < num; ++i) {
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nub_addr_t wp_addr = GetWatchAddress (debug_state, i);
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- uint32_t byte_mask = bits (debug_state.__wcr [i], 12 , 5 );
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DNBLogThreadedIf (LOG_WATCHPOINTS, " DNBArchImplX86_64::"
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" GetHardwareWatchpointHit() slot: %u "
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- " (addr = 0x%llx; byte_mask = 0x%x)" ,
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- i, static_cast <uint64_t >(wp_addr),
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- byte_mask);
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+ " (addr = 0x%llx, WCR = 0x%llx)" ,
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+ i, wp_addr, debug_state.__wcr [i]);
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if (!IsWatchpointEnabled (debug_state, i))
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continue ;
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- if (bits (wp_addr, 48 , 3 ) != bits (addr, 48 , 3 ))
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- continue ;
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+ // DBGWCR<n>EL1.BAS are the bits of the doubleword that are watched
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+ // with a BAS watchpoint.
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+ uint32_t bas_bits = bits (debug_state.__wcr [i], 12 , 5 );
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+ // DBGWCR<n>EL1.MASK is the number of bits that are masked off the
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+ // virtual address when comparing to DBGWVR<n>_EL1.
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+ uint32_t mask = bits (debug_state.__wcr [i], 28 , 24 );
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- // Sanity check the byte_mask
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- uint32_t lsb = LowestBitSet (byte_mask);
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- if (lsb < 0 )
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- continue ;
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+ const bool is_bas_watchpoint = mask == 0 ;
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- uint64_t byte_to_match = bits (addr, 2 , 0 );
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+ DNBLogThreadedIf (
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+ LOG_WATCHPOINTS,
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+ " DNBArchImplARM64::"
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+ " GetHardwareWatchpointHit() slot: %u %s" ,
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+ i, is_bas_watchpoint ? " is BAS watchpoint" : " is MASK watchpoint" );
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- if (byte_mask & (1 << byte_to_match)) {
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- addr = wp_addr + lsb;
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- return i;
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+ if (is_bas_watchpoint) {
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+ if (bits (wp_addr, 48 , 3 ) != bits (addr, 48 , 3 ))
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+ continue ;
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+ } else {
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+ if (bits (wp_addr, 48 , mask) == bits (addr, 48 , mask)) {
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+ DNBLogThreadedIf (LOG_WATCHPOINTS,
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+ " DNBArchImplARM64::"
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+ " GetHardwareWatchpointHit() slot: %u matched MASK "
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+ " ignoring %u low bits" ,
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+ i, mask);
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+ return i;
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+ }
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+ }
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+
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+ if (is_bas_watchpoint) {
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+ // Sanity check the bas_bits
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+ uint32_t lsb = LowestBitSet (bas_bits);
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+ if (lsb < 0 )
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+ continue ;
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+
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+ uint64_t byte_to_match = bits (addr, 2 , 0 );
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+
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+ if (bas_bits & (1 << byte_to_match)) {
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+ addr = wp_addr + lsb;
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+ DNBLogThreadedIf (LOG_WATCHPOINTS,
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+ " DNBArchImplARM64::"
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+ " GetHardwareWatchpointHit() slot: %u matched BAS" ,
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+ i);
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+ return i;
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+ }
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}
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}
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}
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