@@ -1824,12 +1824,6 @@ SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM,
18241824 setOperationAction (ISD::MULHS, MVT::i32 , Expand);
18251825 setOperationAction (ISD::MUL, MVT::i32 , Expand);
18261826
1827- setLibcallImpl (RTLIB::MUL_I32, RTLIB::sparc_umul);
1828- setLibcallImpl (RTLIB::SDIV_I32, RTLIB::sparc_div);
1829- setLibcallImpl (RTLIB::UDIV_I32, RTLIB::sparc_udiv);
1830- setLibcallImpl (RTLIB::SREM_I32, RTLIB::sparc_rem);
1831- setLibcallImpl (RTLIB::UREM_I32, RTLIB::sparc_urem);
1832-
18331827 if (Subtarget->useSoftMulDiv ()) {
18341828 // .umul works for both signed and unsigned
18351829 setOperationAction (ISD::SMUL_LOHI, MVT::i32 , Expand);
@@ -1879,13 +1873,6 @@ SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM,
18791873 setOperationAction (ISD::STORE, MVT::f128 , Custom);
18801874 }
18811875
1882- if (!Subtarget->is64Bit ()) {
1883- setLibcallImpl (RTLIB::FPTOSINT_F128_I64, RTLIB::_Q_qtoll);
1884- setLibcallImpl (RTLIB::FPTOUINT_F128_I64, RTLIB::_Q_qtoull);
1885- setLibcallImpl (RTLIB::SINTTOFP_I64_F128, RTLIB::_Q_lltoq);
1886- setLibcallImpl (RTLIB::UINTTOFP_I64_F128, RTLIB::_Q_ulltoq);
1887- }
1888-
18891876 if (Subtarget->hasHardQuad ()) {
18901877 setOperationAction (ISD::FADD, MVT::f128 , Legal);
18911878 setOperationAction (ISD::FSUB, MVT::f128 , Legal);
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