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fhossein-quickaushik-quicinc
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kaushik-quicinc
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[Hexagon] Support lowering of setuo & seto for vector types in Hexagon (llvm#158740)
Resolves instruction selection failure for v64f16 and v32f32 vector types. Patch by: Fateme Hosseini --------- Co-authored-by: Kaushik Kulkarni <[email protected]>
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‎llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp‎

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@@ -359,6 +359,8 @@ HexagonTargetLowering::initializeHVXLowering() {
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setCondCodeAction(ISD::SETULE, MVT::v64f16, Expand);
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setCondCodeAction(ISD::SETUGE, MVT::v64f16, Expand);
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setCondCodeAction(ISD::SETULT, MVT::v64f16, Expand);
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setCondCodeAction(ISD::SETUO, MVT::v64f16, Expand);
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setCondCodeAction(ISD::SETO, MVT::v64f16, Expand);
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setCondCodeAction(ISD::SETNE, MVT::v32f32, Expand);
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setCondCodeAction(ISD::SETLE, MVT::v32f32, Expand);
@@ -372,6 +374,8 @@ HexagonTargetLowering::initializeHVXLowering() {
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setCondCodeAction(ISD::SETULE, MVT::v32f32, Expand);
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setCondCodeAction(ISD::SETUGE, MVT::v32f32, Expand);
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setCondCodeAction(ISD::SETULT, MVT::v32f32, Expand);
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setCondCodeAction(ISD::SETUO, MVT::v32f32, Expand);
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setCondCodeAction(ISD::SETO, MVT::v32f32, Expand);
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// Boolean vectors.
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‎llvm/test/CodeGen/Hexagon/inst_setcc_uno_uo.ll‎

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;; RUN: llc --mtriple=hexagon -mattr=+hvxv79,+hvx-length128b %s -o - | FileCheck %s
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define dso_local void @store_isnan_f32(ptr %a, ptr %b, ptr %isnan_cmp) local_unnamed_addr {
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entry:
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%arrayidx_a = getelementptr inbounds nuw float, ptr %a, i32 0
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%arrayidx_b = getelementptr inbounds nuw float, ptr %b, i32 0
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%0 = load <32 x float>, ptr %arrayidx_a, align 4
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%1 = load <32 x float>, ptr %arrayidx_b, align 4
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%.vectorized = fcmp uno <32 x float> %0, %1
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%.LS.instance = zext <32 x i1> %.vectorized to <32 x i32>
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%arrayidx1 = getelementptr inbounds nuw i32, ptr %isnan_cmp, i32 0
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store <32 x i32> %.LS.instance, ptr %arrayidx1, align 4
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ret void
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}
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; CHECK: store_isnan_f32
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; CHECK: [[RONE32:r[0-9]+]] = #1
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; CHECK: [[VOP2_F32:v[0-9]+]] = vxor([[VOP2_F32]],[[VOP2_F32]])
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; CHECK: [[VOP1_F32:v[0-9]+]] = vmemu(r0+#0)
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; CHECK: [[VONES32:v[0-9]+]] = vsplat([[RONE32]])
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; CHECK: [[Q1_F32:q[0-9]+]] = vcmp.eq([[VOP1_F32]].w,[[VOP1_F32]].w)
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; CHECK: [[VOP3_F32:v[0-9]+]] = vmemu(r1+#0)
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; CHECK: [[Q1_F32]] &= vcmp.eq([[VOP3_F32]].w,[[VOP3_F32]].w)
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; CHECK: [[VOUT_F32:v[0-9]+]] = vmux([[Q1_F32]],[[VOP2_F32]],[[VONES32]])
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; CHECK: vmemu(r2+#0) = [[VOUT_F32]]
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define dso_local void @store_isnan_f16(ptr %a, ptr %b, ptr %isnan_cmp) local_unnamed_addr {
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entry:
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%arrayidx_a = getelementptr inbounds nuw half, ptr %a, i32 0
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%arrayidx_b = getelementptr inbounds nuw half, ptr %b, i32 0
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%0 = load <64 x half>, ptr %arrayidx_a, align 2
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%1 = load <64 x half>, ptr %arrayidx_b, align 2
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%.vectorized = fcmp uno <64 x half> %0, %1
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%conv.LS.instance = zext <64 x i1> %.vectorized to <64 x i16>
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%arrayidx1 = getelementptr inbounds nuw i16, ptr %isnan_cmp, i32 0
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store <64 x i16> %conv.LS.instance, ptr %arrayidx1, align 2
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ret void
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}
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; CHECK-LABEL: store_isnan_f16
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; CHECK: [[RONE16:r[0-9]+]] = #1
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; CHECK: [[VOP2_F16:v[0-9]+]] = vxor([[VOP2_F16]],[[VOP2_F16]])
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; CHECK: [[VOP1_F16:v[0-9]+]] = vmemu(r0+#0)
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; CHECK: [[VONES16:v[0-9]+]].h = vsplat([[RONE16]])
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; CHECK: [[Q1_F16:q[0-9]+]] = vcmp.eq([[VOP1_F16]].h,[[VOP1_F16]].h)
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; CHECK: [[VOP3_F16:v[0-9]+]] = vmemu(r1+#0)
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; CHECK: [[Q1_F16]] &= vcmp.eq([[VOP3_F16]].h,[[VOP3_F16]].h)
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; CHECK: [[VOUT_F16:v[0-9]+]] = vmux([[Q1_F16]],[[VOP2_F16]],[[VONES16]])
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; CHECK: vmemu(r2+#0) = [[VOUT_F32]]
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define dso_local void @store_isordered_f32(ptr %a, ptr %b, ptr %isordered_cmp) local_unnamed_addr {
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entry:
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%arrayidx_a = getelementptr inbounds nuw float, ptr %a, i32 0
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%arrayidx_b = getelementptr inbounds nuw float, ptr %b, i32 0
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%0 = load <32 x float>, ptr %arrayidx_a, align 4
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%1 = load <32 x float>, ptr %arrayidx_b, align 4
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%.vectorized = fcmp ord <32 x float> %0, %1
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%.LS.instance = zext <32 x i1> %.vectorized to <32 x i32>
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%arrayidx1 = getelementptr inbounds nuw i32, ptr %isordered_cmp, i32 0
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store <32 x i32> %.LS.instance, ptr %arrayidx1, align 4
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ret void
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}
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; CHECK-LABEL: store_isordered_f32
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; CHECK: [[VOP2_ORD_F32:v[0-9]+]] = vxor([[VOP2_ORD_F32]],[[VOP2_ORD_F32]])
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; CHECK: [[VOP1_ORD_F32:v[0-9]+]] = vmemu(r0+#0)
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; CHECK: [[VONES_ORD_F32:v[0-9]+]] = vsplat([[RONE32]])
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; CHECK: [[Q1_ORD_F32:q[0-9]+]] = vcmp.eq([[VOP1_ORD_F32]].w,[[VOP1_ORD_F32]].w)
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; CHECK: [[VOP3_ORD_F32:v[0-9]+]] = vmemu(r1+#0)
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; CHECK: [[Q1_ORD_F32]] &= vcmp.eq([[VOP3_ORD_F32]].w,[[VOP3_ORD_F32]].w)
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; CHECK: [[VOUT_ORD_F32:v[0-9]+]] = vmux([[Q1_ORD_F32]],[[VONES_ORD_F32]],[[VOP2_ORD_F32]])
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; CHECK: vmemu(r2+#0) = [[VOUT_ORD_F32]]
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define dso_local void @store_isordered_f16(ptr %a, ptr %b, ptr %isordered_cmp) local_unnamed_addr {
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entry:
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%arrayidx_a = getelementptr inbounds nuw half, ptr %a, i32 0
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%arrayidx_b = getelementptr inbounds nuw half, ptr %b, i32 0
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%0 = load <64 x half>, ptr %arrayidx_a, align 2
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%1 = load <64 x half>, ptr %arrayidx_b, align 2
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%.vectorized = fcmp ord <64 x half> %0, %1
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%conv.LS.instance = zext <64 x i1> %.vectorized to <64 x i16>
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%arrayidx1 = getelementptr inbounds nuw i16, ptr %isordered_cmp, i32 0
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store <64 x i16> %conv.LS.instance, ptr %arrayidx1, align 2
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ret void
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}
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; CHECK-LABEL: store_isordered_f16
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; CHECK: [[VOP2_ORD_F16:v[0-9]+]] = vxor([[VOP2_ORD_F16]],[[VOP2_ORD_F16]])
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; CHECK: [[VOP1_ORD_F16:v[0-9]+]] = vmemu(r0+#0)
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; CHECK: [[VONES_ORD_F16:v[0-9]+]].h = vsplat([[RONE16]])
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; CHECK: [[Q1_ORD_F16:q[0-9]+]] = vcmp.eq([[VOP1_ORD_F16]].h,[[VOP1_ORD_F16]].h)
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; CHECK: [[VOP3_ORD_F16:v[0-9]+]] = vmemu(r1+#0)
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; CHECK: [[Q1_ORD_F16]] &= vcmp.eq([[VOP3_ORD_F16]].h,[[VOP3_ORD_F16]].h)
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; CHECK: [[VOUT_ORD_F16:v[0-9]+]] = vmux([[Q1_ORD_F16]],[[VONES_ORD_F16]],[[VOP2_ORD_F16]])
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; CHECK: vmemu(r2+#0) = [[VOUT_ORD_F16]]

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