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Merge commit 'b11b8423a9b0' from llvm.org/main into next
2 parents a487480 + b11b842 commit c1e1f11

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llvm/test/CodeGen/RISCV/float-imm.ll

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; RUN: llc -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs < %s \
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; RUN: -target-abi=lp64 | FileCheck --check-prefixes=CHECKZFINX,RV64ZFINX %s
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; TODO: constant pool shouldn't be necessary for RV64IF.
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define float @float_imm() nounwind {
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; CHECK-LABEL: float_imm:
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; CHECK: # %bb.0:

llvm/test/CodeGen/RISCV/half-imm.ll

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; RUN: -target-abi lp64 < %s \
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; RUN: | FileCheck -check-prefixes=CHECKIZHINXMIN,RV64IZHINXMIN %s
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; TODO: constant pool shouldn't be necessary for RV32IZfh and RV64IZfh
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define half @half_imm() nounwind {
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; CHECK-LABEL: half_imm:
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; CHECK: # %bb.0:

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