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2 parents b143c12 + 8284e4d commit d18cb4fCopy full SHA for d18cb4f
llvm/lib/Target/RISCV/RISCVGISel.td
@@ -126,8 +126,6 @@ let Predicates = [HasAtomicLdSt, IsRV64] in {
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// RV64 i32 patterns not used by SelectionDAG
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//===----------------------------------------------------------------------===//
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-def uimm5i32 : ImmLeaf<i32, [{return isUInt<5>(Imm);}]>;
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-
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def zext_is_sext : PatFrag<(ops node:$src), (zext node:$src), [{
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KnownBits Known = CurDAG->computeKnownBits(N->getOperand(0), 0);
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return Known.isNonNegative();
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