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[IRGen] Use at least Int8 for extra tag bits
rdar://149985633 Using at least Int8 here allows LLVM to apply more optimizations, reducing code size, avoiding stack allocations and as a result often eliminating complete stack frames.
1 parent 1bff8cd commit 48ee212

16 files changed

+152
-117
lines changed

‎lib/IRGen/GenEnum.cpp‎

Lines changed: 10 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -1430,10 +1430,7 @@ namespace {
14301430
// types other than i1 or power-of-two-byte sizes like i8, i16, etc. inhibit
14311431
// FastISel and expose backend bugs.
14321432
static unsigned getIntegerBitSizeForTag(unsigned tagBits) {
1433-
// i1 is used to represent bool in C so is fairly well supported.
1434-
if (tagBits == 1)
1435-
return 1;
1436-
// Otherwise, round the physical size in bytes up to the next power of two.
1433+
// Round the physical size in bytes up to the next power of two.
14371434
unsigned tagBytes = (tagBits + 7U)/8U;
14381435
if (!llvm::isPowerOf2_32(tagBytes))
14391436
tagBytes = llvm::NextPowerOf2(tagBytes);
@@ -2221,15 +2218,9 @@ namespace {
22212218
// If any tag bits are present, they must match.
22222219
llvm::Value *tagResult = nullptr;
22232220
if (tagBits) {
2224-
if (ExtraTagBitCount == 1) {
2225-
if (extraTag == 1)
2226-
tagResult = tagBits;
2227-
else
2228-
tagResult = IGF.Builder.CreateNot(tagBits);
2229-
} else {
2230-
tagResult = IGF.Builder.CreateICmpEQ(tagBits,
2231-
llvm::ConstantInt::get(IGF.IGM.getLLVMContext(), extraTag));
2232-
}
2221+
tagResult = IGF.Builder.CreateICmpEQ(
2222+
tagBits,
2223+
llvm::ConstantInt::get(IGF.IGM.getLLVMContext(), extraTag));
22332224
}
22342225

22352226
if (tagResult && payloadResult)
@@ -2311,7 +2302,9 @@ namespace {
23112302
oneDest = llvm::BasicBlock::Create(C);
23122303
tagBitBlocks.push_back(oneDest);
23132304
}
2314-
IGF.Builder.CreateCondBr(tagBits, oneDest, zeroDest);
2305+
auto isOne = IGF.Builder.CreateICmpEQ(
2306+
tagBits, llvm::ConstantInt::get(tagBits->getType(), 1));
2307+
IGF.Builder.CreateCondBr(isOne, oneDest, zeroDest);
23152308
} else {
23162309
auto swi = SwitchBuilder::create(IGF, tagBits,
23172310
SwitchDefaultDest(unreachableBB, IsUnreachable),
@@ -2587,14 +2580,9 @@ namespace {
25872580
// If we have extra tag bits, they will be zero if we contain a payload.
25882581
if (ExtraTagBitCount > 0) {
25892582
assert(extraBits);
2590-
llvm::Value *isNonzero;
2591-
if (ExtraTagBitCount == 1) {
2592-
isNonzero = extraBits;
2593-
} else {
2594-
llvm::Value *zero = llvm::ConstantInt::get(extraBits->getType(), 0);
2595-
isNonzero = IGF.Builder.CreateICmp(llvm::CmpInst::ICMP_NE,
2596-
extraBits, zero);
2597-
}
2583+
llvm::Value *zero = llvm::ConstantInt::get(extraBits->getType(), 0);
2584+
llvm::Value *isNonzero =
2585+
IGF.Builder.CreateICmp(llvm::CmpInst::ICMP_NE, extraBits, zero);
25982586

25992587
auto *zeroBB = llvm::BasicBlock::Create(IGF.IGM.getLLVMContext());
26002588
IGF.Builder.CreateCondBr(isNonzero, nonzeroBB, zeroBB);

‎test/IRGen/alignment.sil‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -57,10 +57,10 @@ entry:
5757
store %w to %d : $*NoPayload
5858

5959
// CHECK: load i32{{.*}}, align 16
60-
// CHECK: load i1{{.*}}, align 4
60+
// CHECK: load i8{{.*}}, align 4
6161
%v = load %e : $*SinglePayload
6262
// CHECK: store i32{{.*}}, align 16
63-
// CHECK: store i1{{.*}}, align 4
63+
// CHECK: store i8{{.*}}, align 4
6464
store %v to %e : $*SinglePayload
6565

6666
// CHECK: load i32{{.*}}, align 16

‎test/IRGen/bitcast.sil‎

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -40,11 +40,9 @@ entry(%c : $C):
4040

4141
// CHECK-x86_64-LABEL: define{{( dllexport)?}}{{( protected)?}} swiftcc { i64, i8 } @bitcast_trivial_optional(i64 %0, i8 %1) {{.*}} {
4242
// CHECK-x86_64-NEXT: entry:
43-
// CHECK-x86_64-NEXT: %2 = trunc i8 %1 to i1
44-
// CHECK-x86_64-NEXT: %3 = zext i1 %2 to i8
45-
// CHECK-x86_64-NEXT: %4 = insertvalue { i64, i8 } undef, i64 %0, 0
46-
// CHECK-x86_64-NEXT: %5 = insertvalue { i64, i8 } %4, i8 %3, 1
47-
// CHECK-x86_64-NEXT: ret { i64, i8 } %5
43+
// CHECK-x86_64-NEXT: %2 = insertvalue { i64, i8 } undef, i64 %0, 0
44+
// CHECK-x86_64-NEXT: %3 = insertvalue { i64, i8 } %2, i8 %1, 1
45+
// CHECK-x86_64-NEXT: ret { i64, i8 } %3
4846

4947
sil @bitcast_trivial_optional: $@convention(thin) (Optional<Int>) -> Optional<Int> {
5048
entry(%c : $Optional<Int>):

‎test/IRGen/enum.sil‎

Lines changed: 20 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -470,10 +470,10 @@ enum SinglePayloadNoXI2 {
470470
// CHECK-32: define{{( dllexport)?}}{{( protected)?}} swiftcc i1 @select_enum([[WORD:i32]] %0, i8 %1)
471471
// CHECK-64: define{{( dllexport)?}}{{( protected)?}} swiftcc i1 @select_enum([[WORD:i64]] %0, i8 %1)
472472
// CHECK: entry:
473-
// CHECK: [[TAG:%.*]] = trunc i8 %1 to i1
474473
// CHECK: [[PAYLOAD:%.*]] = icmp eq [[WORD]] %0, 1
475-
// CHECK: [[MATCHES:%.*]] = and i1 [[TAG]], [[PAYLOAD]]
476-
// CHECK: [[RES:%.*]] = select i1 [[MATCHES]], i1 false, i1 true
474+
// CHECK: [[TAG:%.*]] = icmp eq i8 %1, 1
475+
// CHECK: [[COMBINED:%.*]] = and i1 [[TAG]], [[PAYLOAD]]
476+
// CHECK: [[RES:%.*]] = select i1 [[COMBINED]], i1 false, i1 true
477477
// CHECK: ret i1 [[RES]]
478478
// CHECK: }
479479

@@ -490,7 +490,7 @@ bb0(%0 : $SinglePayloadNoXI2):
490490
sil @single_payload_no_xi_switch : $@convention(thin) (SinglePayloadNoXI2) -> () {
491491
// CHECK: entry:
492492
entry(%u : $SinglePayloadNoXI2):
493-
// CHECK: %2 = trunc i8
493+
// CHECK: %2 = icmp eq i8 %1, 1
494494
// CHECK: br i1 %2, label %[[TAGS:[0-9]+]], label %[[X_DEST:[0-9]+]]
495495
// CHECK: [[TAGS]]:
496496
// CHECK: switch [[WORD]] %0, label %[[DFLT:[0-9]+]] [
@@ -564,7 +564,7 @@ end:
564564
sil @single_payload_no_xi_switch_arg : $@convention(thin) (SinglePayloadNoXI2) -> () {
565565
// CHECK: entry:
566566
entry(%u : $SinglePayloadNoXI2):
567-
// CHECK: %2 = trunc i8
567+
// CHECK: %2 = icmp eq i8 %1, 1
568568
// CHECK: br i1 %2, label %[[TAGS:[0-9]+]], label %[[X_PREDEST:[0-9]+]]
569569
// CHECK: [[TAGS]]:
570570
// CHECK: switch [[WORD]] %0, label %[[DFLT:[0-9]+]] [
@@ -633,7 +633,7 @@ entry(%0 : $Builtin.Word):
633633
// CHECK: entry:
634634
// CHECK: store [[WORD]] %0, ptr %1
635635
// CHECK: [[T0:%.*]] = getelementptr inbounds %T4enum18SinglePayloadNoXI2O, ptr %1, i32 0, i32 1
636-
// CHECK: store i1 false, ptr [[T0]]
636+
// CHECK: store i8 0, ptr [[T0]]
637637
// CHECK: ret void
638638
// CHECK: }
639639
sil @single_payload_no_xi_inject_x_indirect : $(Builtin.Word, @inout SinglePayloadNoXI2) -> () {
@@ -659,7 +659,7 @@ entry:
659659
// CHECK: entry:
660660
// CHECK: store [[WORD]] 0, ptr %0
661661
// CHECK: [[T0:%.*]] = getelementptr inbounds %T4enum18SinglePayloadNoXI2O, ptr %0, i32 0, i32 1
662-
// CHECK: store i1 true, ptr [[T0]]
662+
// CHECK: store i8 1, ptr [[T0]]
663663
// CHECK: ret void
664664
// CHECK: }
665665
sil @single_payload_no_xi_inject_y_indirect : $(@inout SinglePayloadNoXI2) -> () {
@@ -1593,12 +1593,10 @@ enum MultiPayloadOneSpareBit {
15931593
// CHECK-64: define{{( dllexport)?}}{{( protected)?}} swiftcc void @multi_payload_one_spare_bit_switch(i64 %0, i8 %1) {{.*}} {
15941594
sil @multi_payload_one_spare_bit_switch : $(MultiPayloadOneSpareBit) -> () {
15951595
entry(%u : $MultiPayloadOneSpareBit):
1596-
// CHECK-64: [[NATIVECC_TRUNC:%.*]] = trunc i8 %1 to i1
15971596
// CHECK-64: [[SPARE_TAG_LSHR:%.*]] = lshr i64 %0, 63
15981597
// CHECK-64: [[SPARE_TAG_TRUNC:%.*]] = trunc i64 [[SPARE_TAG_LSHR]] to i8
15991598
// CHECK-64: [[SPARE_TAG:%.*]] = and i8 [[SPARE_TAG_TRUNC]], 1
1600-
// CHECK-64: [[EXTRA_TAG_ZEXT:%.*]] = zext i1 [[NATIVECC_TRUNC]] to i8
1601-
// CHECK-64: [[EXTRA_TAG:%.*]] = shl i8 [[EXTRA_TAG_ZEXT]], 1
1599+
// CHECK-64: [[EXTRA_TAG:%.*]] = shl i8 %1, 1
16021600
// CHECK-64: [[TAG:%.*]] = or i8 [[SPARE_TAG]], [[EXTRA_TAG]]
16031601
// CHECK-64: switch i8 [[TAG]], label %[[UNREACHABLE:[0-9]+]] [
16041602
// CHECK-64: i8 0, label %[[X_PREDEST:[0-9]+]]
@@ -1681,7 +1679,7 @@ sil @multi_payload_one_spare_bit_switch_indirect : $(@inout MultiPayloadOneSpare
16811679
entry(%u : $*MultiPayloadOneSpareBit):
16821680
// CHECK-64: [[PAYLOAD:%.*]] = load i64, ptr %0
16831681
// CHECK-64: [[T0:%.*]] = getelementptr inbounds %T4enum23MultiPayloadOneSpareBitO, ptr %0, i32 0, i32 1
1684-
// CHECK-64: [[TAG:%.*]] = load i1, ptr [[T0]]
1682+
// CHECK-64: [[TAG:%.*]] = load i8, ptr [[T0]]
16851683
// CHECK-64: switch i8 {{%.*}}
16861684
// CHECK-64: switch i64 [[PAYLOAD]]
16871685
// CHECK-64: {{[0-9]+}}:
@@ -1748,7 +1746,7 @@ entry(%0 : $Builtin.Int62):
17481746
// CHECK-64: [[PAYLOAD_MASKED:%.*]] = and i64 [[PAYLOAD]], 9223372036854775807
17491747
// CHECK-64: store i64 [[PAYLOAD_MASKED]], ptr %1
17501748
// CHECK-64: [[T0:%.*]] = getelementptr inbounds %T4enum23MultiPayloadOneSpareBitO, ptr %1, i32 0, i32 1
1751-
// CHECK-64: store i1 false, ptr [[T0]]
1749+
// CHECK-64: store i8 0, ptr [[T0]]
17521750
// CHECK-64: ret void
17531751
// CHECK-64: }
17541752
sil @multi_payload_one_spare_bit_inject_x_indirect : $(Builtin.Int62, @inout MultiPayloadOneSpareBit) -> () {
@@ -1788,7 +1786,7 @@ entry(%0 : $Builtin.Int63):
17881786
// CHECK-64: [[PAYLOAD_TAGGED:%.*]] = or i64 [[PAYLOAD_MASKED]], -9223372036854775808
17891787
// CHECK-64: store i64 [[PAYLOAD_TAGGED]], ptr %1
17901788
// CHECK-64: [[T0:%.*]] = getelementptr inbounds %T4enum23MultiPayloadOneSpareBitO, ptr %1, i32 0, i32 1
1791-
// CHECK-64: store i1 false, ptr [[T0]]
1789+
// CHECK-64: store i8 0, ptr [[T0]]
17921790
// CHECK-64: ret void
17931791
// CHECK-64: }
17941792

@@ -1831,7 +1829,7 @@ entry:
18311829
// -- 0x8000_0000_0000_0000
18321830
// CHECK-64: store i64 -9223372036854775808, ptr %0
18331831
// CHECK-64: [[T0:%.*]] = getelementptr inbounds %T4enum23MultiPayloadOneSpareBitO, ptr %0, i32 0, i32 1
1834-
// CHECK-64: store i1 true, ptr [[T0]]
1832+
// CHECK-64: store i8 1, ptr [[T0]]
18351833
// CHECK-64: ret void
18361834
// CHECK-64: }
18371835
sil @multi_payload_one_spare_bit_inject_a_indirect : $(@inout MultiPayloadOneSpareBit) -> () {
@@ -2227,8 +2225,9 @@ enum MultiPayloadNested {
22272225
// CHECK: %3 = getelementptr
22282226
// CHECK: %4 = load i8, ptr %3
22292227
// CHECK: %5 = lshr i8 %4, 7
2230-
// CHECK: %6 = trunc i8 %5 to i1
2231-
// CHECK: br i1 %6
2228+
// CHECK: %6 = and i8 %5, 1
2229+
// CHECK: %7 = icmp ne i8 %6, 1
2230+
// CHECK: br i1 %7
22322231
sil @multi_payload_nested_switch : $(@in MultiPayloadNested) -> () {
22332232
entry(%c : $*MultiPayloadNested):
22342233
switch_enum_addr %c : $*MultiPayloadNested, case #MultiPayloadNested.A!enumelt: a_dest, case #MultiPayloadNested.B!enumelt: b_dest
@@ -2259,8 +2258,10 @@ enum MultiPayloadNestedSpareBits {
22592258
// CHECK-64: entry:
22602259
// CHECK-64: %1 = load [[WORD]], ptr %0
22612260
// CHECK-64: %2 = lshr [[WORD]] %1, 61
2262-
// CHECK-64: %3 = trunc [[WORD]] %2 to i1
2263-
// CHECK-64: br i1 %3
2261+
// CHECK-64: %3 = trunc [[WORD]] %2 to i8
2262+
// CHECK-64: %4 = and i8 %3, 1
2263+
// CHECK-64: %5 = icmp ne i8 %4, 1
2264+
// CHECK-64: br i1 %5
22642265
sil @multi_payload_nested_spare_bits_switch : $(@in MultiPayloadNestedSpareBits) -> () {
22652266
entry(%c : $*MultiPayloadNestedSpareBits):
22662267
switch_enum_addr %c : $*MultiPayloadNestedSpareBits, case #MultiPayloadNestedSpareBits.A!enumelt: a_dest, case #MultiPayloadNestedSpareBits.B!enumelt: b_dest
@@ -2459,7 +2460,7 @@ entry(%x : $Int32):
24592460
// CHECK-64: [[INT_ZEXT:%.*]] = zext i32 %0 to i64
24602461
// CHECK-64: [[INT_SHL:%.*]] = shl i64 [[INT_ZEXT]], 32
24612462
%d = enum $Optional<(Optional<()>, Int32)>, #Optional.some!enumelt, %c : $(Optional<()>, Int32)
2462-
// CHECK-64: [[BIT:%.*]] = trunc i64 [[INT_SHL]] to i1
2463+
// CHECK-64: [[BIT:%.*]] = trunc i64 [[INT_SHL]] to i8
24632464
// CHECK-64: [[INT_SHR:%.*]] = lshr i64 [[INT_SHL]], 32
24642465
// CHECK-64: [[INT:%.*]] = trunc i64 [[INT_SHR]] to i32
24652466
%e = unchecked_enum_data %d : $Optional<(Optional<()>, Int32)>, #Optional.some!enumelt

‎test/IRGen/enum_copy_init_with_take_memcpy.swift‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -30,9 +30,9 @@ struct HasAnEnum {
3030
// CHECK: define {{.*}} swiftcc range(i64 -1, 5) i64 @"$s31enum_copy_init_with_take_memcpy9HasAnEnumV9readValueSiyF"(ptr {{.*}} %0)
3131
// CHECK: [[T0:%.*]] = getelementptr inbounds i8, ptr %0, i64 160
3232
// CHECK: [[T1:%.*]] = load i8, ptr [[T0]]
33-
// CHECK: [[T2:%.*]] = icmp eq i8 [[T1]], 2
34-
// CHECK: br i1 [[T2]], label
35-
// CHECK: [[R:%.*]] = phi i64 [ -1, {{.*}} ], [ 4, {{.*}} ]
33+
// CHECK: [[T2:%.*]] = and i8 [[T1]], -3
34+
// CHECK: [[T3:%.*]] = icmp eq i8 [[T2]], 0
35+
// CHECK: [[R:%.*]] = select i1 [[T3]], i64 -1, i64 4
3636
// CHECK: ret i64 [[R]]
3737

3838
}

‎test/IRGen/enum_dynamic_multi_payload.sil‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -40,21 +40,21 @@ entry(%e : $Either<(), ()>):
4040
fix_lifetime %e : $Either<(), ()>
4141

4242
// CHECK-NEXT: alloca
43-
// CHECK-NEXT: trunc i8 {{.*}} to i1
4443
// CHECK-NEXT: llvm.lifetime.start
4544
%s = alloc_stack $Either<(), ()>
4645

4746
%l = enum $Either<(), ()>, #Either.Left!enumelt, undef : $()
48-
// CHECK-NEXT: store i1 false
47+
// CHECK-NEXT: store i8 0
4948
store %l to %s : $*Either<(), ()>
5049
%r = enum $Either<(), ()>, #Either.Right!enumelt, undef : $()
51-
// CHECK-NEXT: store i1 true
50+
// CHECK-NEXT: store i8 1
51+
// CHECK-NEXT: [[COND:%.*]] = icmp ne i8 {{%.*}}, 1
5252
store %r to %s : $*Either<(), ()>
5353

5454
%a = unchecked_enum_data %l : $Either<(), ()>, #Either.Left!enumelt
5555
%b = unchecked_enum_data %r : $Either<(), ()>, #Either.Right!enumelt
5656

57-
// CHECK-NEXT: br i1 {{%.*}}, label %[[RIGHT_PRE:[0-9]+]], label %[[LEFT_PRE:[0-9]+]]
57+
// CHECK-NEXT: br i1 [[COND]], label %[[LEFT_PRE:[0-9]+]], label %[[RIGHT_PRE:[0-9]+]]
5858
// CHECK: [[LEFT_PRE]]:
5959
// CHECK: br label [[LEFT:%[0-9]+]]
6060
// CHECK: [[RIGHT_PRE]]:

‎test/IRGen/enum_future.sil‎

Lines changed: 18 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -474,8 +474,8 @@ enum SinglePayloadNoXI2 {
474474
// CHECK-32: define{{( dllexport)?}}{{( protected)?}} swiftcc i1 @select_enum([[WORD:i32]] %0, i8 %1)
475475
// CHECK-64: define{{( dllexport)?}}{{( protected)?}} swiftcc i1 @select_enum([[WORD:i64]] %0, i8 %1)
476476
// CHECK: entry:
477-
// CHECK: [[TAG:%.*]] = trunc i8 %1 to i1
478477
// CHECK: [[PAYLOAD:%.*]] = icmp eq [[WORD]] %0, 1
478+
// CHECK: [[TAG:%.*]] = icmp eq i8 %1, 1
479479
// CHECK: [[MATCHES:%.*]] = and i1 [[TAG]], [[PAYLOAD]]
480480
// CHECK: [[RES:%.*]] = select i1 [[MATCHES]], i1 false, i1 true
481481
// CHECK: ret i1 [[RES]]
@@ -494,7 +494,7 @@ bb0(%0 : $SinglePayloadNoXI2):
494494
sil @single_payload_no_xi_switch : $@convention(thin) (SinglePayloadNoXI2) -> () {
495495
// CHECK: entry:
496496
entry(%u : $SinglePayloadNoXI2):
497-
// CHECK: %2 = trunc i8
497+
// CHECK: %2 = icmp eq i8 %1, 1
498498
// CHECK: br i1 %2, label %[[TAGS:[0-9]+]], label %[[X_DEST:[0-9]+]]
499499
// CHECK: [[TAGS]]:
500500
// CHECK: switch [[WORD]] %0, label %[[DFLT:[0-9]+]] [
@@ -568,7 +568,7 @@ end:
568568
sil @single_payload_no_xi_switch_arg : $@convention(thin) (SinglePayloadNoXI2) -> () {
569569
// CHECK: entry:
570570
entry(%u : $SinglePayloadNoXI2):
571-
// CHECK: %2 = trunc i8
571+
// CHECK: %2 = icmp eq i8 %1, 1
572572
// CHECK: br i1 %2, label %[[TAGS:[0-9]+]], label %[[X_PREDEST:[0-9]+]]
573573
// CHECK: [[TAGS]]:
574574
// CHECK: switch [[WORD]] %0, label %[[DFLT:[0-9]+]] [
@@ -637,7 +637,7 @@ entry(%0 : $Builtin.Word):
637637
// CHECK: entry:
638638
// CHECK: store [[WORD]] %0, ptr %1
639639
// CHECK: [[T0:%.*]] = getelementptr inbounds %T11enum_future18SinglePayloadNoXI2O, ptr %1, i32 0, i32 1
640-
// CHECK: store i1 false, ptr [[T0]]
640+
// CHECK: store i8 0, ptr [[T0]]
641641
// CHECK: ret void
642642
// CHECK: }
643643
sil @single_payload_no_xi_inject_x_indirect : $(Builtin.Word, @inout SinglePayloadNoXI2) -> () {
@@ -663,7 +663,7 @@ entry:
663663
// CHECK: entry:
664664
// CHECK: store [[WORD]] 0, ptr %0
665665
// CHECK: [[T0:%.*]] = getelementptr inbounds %T11enum_future18SinglePayloadNoXI2O, ptr %0, i32 0, i32 1
666-
// CHECK: store i1 true, ptr [[T0]]
666+
// CHECK: store i8 1, ptr [[T0]]
667667
// CHECK: ret void
668668
// CHECK: }
669669
sil @single_payload_no_xi_inject_y_indirect : $(@inout SinglePayloadNoXI2) -> () {
@@ -1597,12 +1597,10 @@ enum MultiPayloadOneSpareBit {
15971597
// CHECK-64: define{{( dllexport)?}}{{( protected)?}} swiftcc void @multi_payload_one_spare_bit_switch(i64 %0, i8 %1) {{.*}} {
15981598
sil @multi_payload_one_spare_bit_switch : $(MultiPayloadOneSpareBit) -> () {
15991599
entry(%u : $MultiPayloadOneSpareBit):
1600-
// CHECK-64: [[NATIVECC_TRUNC:%.*]] = trunc i8 %1 to i1
16011600
// CHECK-64: [[SPARE_TAG_LSHR:%.*]] = lshr i64 %0, 63
16021601
// CHECK-64: [[SPARE_TAG_TRUNC:%.*]] = trunc i64 [[SPARE_TAG_LSHR]] to i8
16031602
// CHECK-64: [[SPARE_TAG:%.*]] = and i8 [[SPARE_TAG_TRUNC]], 1
1604-
// CHECK-64: [[EXTRA_TAG_ZEXT:%.*]] = zext i1 [[NATIVECC_TRUNC]] to i8
1605-
// CHECK-64: [[EXTRA_TAG:%.*]] = shl i8 [[EXTRA_TAG_ZEXT]], 1
1603+
// CHECK-64: [[EXTRA_TAG:%.*]] = shl i8 %1, 1
16061604
// CHECK-64: [[TAG:%.*]] = or i8 [[SPARE_TAG]], [[EXTRA_TAG]]
16071605
// CHECK-64: switch i8 [[TAG]], label %[[UNREACHABLE:[0-9]+]] [
16081606
// CHECK-64: i8 0, label %[[X_PREDEST:[0-9]+]]
@@ -1685,7 +1683,7 @@ sil @multi_payload_one_spare_bit_switch_indirect : $(@inout MultiPayloadOneSpare
16851683
entry(%u : $*MultiPayloadOneSpareBit):
16861684
// CHECK-64: [[PAYLOAD:%.*]] = load i64, ptr %0
16871685
// CHECK-64: [[T0:%.*]] = getelementptr inbounds %T11enum_future23MultiPayloadOneSpareBitO, ptr %0, i32 0, i32 1
1688-
// CHECK-64: [[TAG:%.*]] = load i1, ptr [[T0]]
1686+
// CHECK-64: [[TAG:%.*]] = load i8, ptr [[T0]]
16891687
// CHECK-64: switch i8 {{%.*}}
16901688
// CHECK-64: switch i64 [[PAYLOAD]]
16911689
// CHECK-64: {{[0-9]+}}:
@@ -1752,7 +1750,7 @@ entry(%0 : $Builtin.Int62):
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// CHECK-64: [[PAYLOAD_MASKED:%.*]] = and i64 [[PAYLOAD]], 9223372036854775807
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// CHECK-64: store i64 [[PAYLOAD_MASKED]], ptr %1
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// CHECK-64: [[T0:%.*]] = getelementptr inbounds %T11enum_future23MultiPayloadOneSpareBitO, ptr %1, i32 0, i32 1
1755-
// CHECK-64: store i1 false, ptr [[T0]]
1753+
// CHECK-64: store i8 0, ptr [[T0]]
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// CHECK-64: ret void
17571755
// CHECK-64: }
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sil @multi_payload_one_spare_bit_inject_x_indirect : $(Builtin.Int62, @inout MultiPayloadOneSpareBit) -> () {
@@ -1792,7 +1790,7 @@ entry(%0 : $Builtin.Int63):
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// CHECK-64: [[PAYLOAD_TAGGED:%.*]] = or i64 [[PAYLOAD_MASKED]], -9223372036854775808
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// CHECK-64: store i64 [[PAYLOAD_TAGGED]], ptr %1
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// CHECK-64: [[T0:%.*]] = getelementptr inbounds %T11enum_future23MultiPayloadOneSpareBitO, ptr %1, i32 0, i32 1
1795-
// CHECK-64: store i1 false, ptr [[T0]]
1793+
// CHECK-64: store i8 0, ptr [[T0]]
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// CHECK-64: ret void
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// CHECK-64: }
17981796

@@ -1835,7 +1833,7 @@ entry:
18351833
// -- 0x8000_0000_0000_0000
18361834
// CHECK-64: store i64 -9223372036854775808, ptr %0
18371835
// CHECK-64: [[T0:%.*]] = getelementptr inbounds %T11enum_future23MultiPayloadOneSpareBitO, ptr %0, i32 0, i32 1
1838-
// CHECK-64: store i1 true, ptr [[T0]]
1836+
// CHECK-64: store i8 1, ptr [[T0]]
18391837
// CHECK-64: ret void
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// CHECK-64: }
18411839
sil @multi_payload_one_spare_bit_inject_a_indirect : $(@inout MultiPayloadOneSpareBit) -> () {
@@ -2231,8 +2229,9 @@ enum MultiPayloadNested {
22312229
// CHECK: %3 = getelementptr
22322230
// CHECK: %4 = load i8, ptr %3
22332231
// CHECK: %5 = lshr i8 %4, 7
2234-
// CHECK: %6 = trunc i8 %5 to i1
2235-
// CHECK: br i1 %6
2232+
// CHECK: %6 = and i8 %5, 1
2233+
// CHECK: %7 = icmp ne i8 %6, 1
2234+
// CHECK: br i1 %7
22362235
sil @multi_payload_nested_switch : $(@in MultiPayloadNested) -> () {
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entry(%c : $*MultiPayloadNested):
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switch_enum_addr %c : $*MultiPayloadNested, case #MultiPayloadNested.A!enumelt: a_dest, case #MultiPayloadNested.B!enumelt: b_dest
@@ -2263,8 +2262,10 @@ enum MultiPayloadNestedSpareBits {
22632262
// CHECK-64: entry:
22642263
// CHECK-64: %1 = load [[WORD]], ptr %0
22652264
// CHECK-64: %2 = lshr [[WORD]] %1, 61
2266-
// CHECK-64: %3 = trunc [[WORD]] %2 to i1
2267-
// CHECK-64: br i1 %3
2265+
// CHECK-64: %3 = trunc [[WORD]] %2 to i8
2266+
// CHECK-64: %4 = and i8 %3, 1
2267+
// CHECK-64: %5 = icmp ne i8 %4, 1
2268+
// CHECK-64: br i1 %5
22682269
sil @multi_payload_nested_spare_bits_switch : $(@in MultiPayloadNestedSpareBits) -> () {
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entry(%c : $*MultiPayloadNestedSpareBits):
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switch_enum_addr %c : $*MultiPayloadNestedSpareBits, case #MultiPayloadNestedSpareBits.A!enumelt: a_dest, case #MultiPayloadNestedSpareBits.B!enumelt: b_dest
@@ -2463,7 +2464,7 @@ entry(%x : $Int32):
24632464
// CHECK-64: [[INT_ZEXT:%.*]] = zext i32 %0 to i64
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// CHECK-64: [[INT_SHL:%.*]] = shl i64 [[INT_ZEXT]], 32
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%d = enum $Optional<(Optional<()>, Int32)>, #Optional.some!enumelt, %c : $(Optional<()>, Int32)
2466-
// CHECK-64: [[BIT:%.*]] = trunc i64 [[INT_SHL]] to i1
2467+
// CHECK-64: [[BIT:%.*]] = trunc i64 [[INT_SHL]] to i8
24672468
// CHECK-64: [[INT_SHR:%.*]] = lshr i64 [[INT_SHL]], 32
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// CHECK-64: [[INT:%.*]] = trunc i64 [[INT_SHR]] to i32
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%e = unchecked_enum_data %d : $Optional<(Optional<()>, Int32)>, #Optional.some!enumelt

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