Fix some IRGen tests on arm64e

Author: aschwaighofer

test/IRGen/async/hop_to_executor.sil

@@ -22,6 +22,9 @@ import _Concurrency
 // CHECK: [[CTX:%[0-9+]+]] = load ptr, ptr [[CTX_ADDR]], align 8
 // CHECK: [[CONT_ADDR:%[0-9]+]] = getelementptr inbounds <{ ptr, ptr }>, ptr [[CTX]], i32 0, i32 1
 // CHECK: [[RET_CONTINUATION:%.*]] = load ptr, ptr [[CONT_ADDR]], align 8
+// CHECK-arm64e:  [[T0:%.*]] = ptrtoint ptr [[RET_CONTINUATION]] to i64
+// CHECK-arm64e:  [[T1:%.*]] = call i64 @llvm.ptrauth.auth(i64 [[T0]]
+// CHECK-arm64e:  [[RET_CONTINUATION:%.*]] = inttoptr i64 [[T1]] to ptr
 // CHECK: call i1 (ptr, i1, ...) @llvm.coro.end.async(ptr {{.*}}, i1 false, ptr @[[TAIL_CALL_FUNC:.*]], ptr [[RET_CONTINUATION]]
 // CHECK: unreachable
 

test/IRGen/enum_resilience.swift

@@ -307,12 +307,12 @@ extension ResilientMultiPayloadGenericEnum {
 // CHECK-LABEL: define{{( dllexport)?}}{{( protected)?}} swiftcc void @"$s15enum_resilience39constructExhaustiveWithResilientMembers010resilient_A011SimpleShapeOyF"(ptr noalias nocapture sret({{.*}}) %0)
 // CHECK: [[T0:%.*]] = call swiftcc %swift.metadata_response @"$s16resilient_struct4SizeVMa"([[INT]] 0)
 // CHECK-NEXT: [[METADATA:%.*]] = extractvalue %swift.metadata_response [[T0]], 0
-// CHECK-arm64e-NEXT: ptrtoint ptr {{.*}} to i64
-// CHECK-arm64e-NEXT: call i64 @llvm.ptrauth.blend
 // CHECK-NEXT: [[WITNESSTABLE_ADDR:%[0-9]+]] = getelementptr inbounds ptr, ptr [[METADATA]], i64 -1
 // CHECK-NEXT: %.valueWitnesses = load ptr, ptr [[WITNESSTABLE_ADDR]]
 // CHECK-NEXT: [[WITNESS_ADDR:%[0-9]+]] = getelementptr inbounds ptr, ptr %.valueWitnesses, i32 7
 // CHECK-NEXT: [[WITNESS_FN:%[0-9]+]] = load ptr, ptr [[WITNESS_ADDR]]
+// CHECK-arm64e-NEXT: ptrtoint ptr {{.*}} to i64
+// CHECK-arm64e-NEXT: call i64 @llvm.ptrauth.blend
 // CHECK-NEXT: call void [[WITNESS_FN]](ptr noalias %0, i32 1, i32 1, ptr [[METADATA]])
 // CHECK-NEXT: ret void
 // CHECK-NEXT: {{^}$}}

test/IRGen/opaque_values_irgen.sil

@@ -7,10 +7,10 @@ sil_stage raw
 // CHECK: define hidden swiftcc void @f010_irgen_identity(ptr noalias nocapture sret({{.*}}) %0, ptr noalias nocapture %1, ptr %T)
 // CHECK: entry:
 // CHECK-NOT: call
-// CHECK-arm64e: call i64 @llvm.ptrauth.blend
 // CHECK-NOT: call
 // CHECK: [[InitializeWithTake_ADDR:%.*]] = getelementptr inbounds ptr, ptr %T.valueWitnesses
 // CHECK: [[InitializeWithTake:%.*]] = load ptr, ptr [[InitializeWithTake_ADDR]]
+// CHECK-arm64e: call i64 @llvm.ptrauth.blend
 // CHECK: %{{.*}} = call ptr [[InitializeWithTake]](ptr noalias %0, ptr noalias %1, ptr %T)
 // CHECK-NOT: call
 // CHECK: ret void

test/IRGen/relative_protocol_witness_table.swift

@@ -252,7 +252,7 @@ func instantiate_conditional_conformance_2nd<T>(_ t : T)  where T: Sub, T.S == T
 // CHECK:[[L2]]:
 // CHECK-arm64e:  [[P0:%.*]] = ptrtoint ptr [[T_INHERITED]] to i64
 // CHECK-arm64e:  [[P1:%.*]] = call i64 @llvm.ptrauth.auth(i64 [[P0]], i32 2, i64 47152)
-// CHECK-arm64e:  [[P2:%.*]] = inttoptr i64 [[P1]] to ptr
+// CHECK-arm64e:  [[T_INHERITED:%.*]] = inttoptr i64 [[P1]] to ptr
 // CHECK:  [[T9:%.*]] = getelementptr inbounds i32, ptr [[T_INHERITED]], i32 1
 // CHECK:  [[T10:%.*]] = load i32, ptr [[T9]]
 // CHECK:  [[T11:%.*]] = sext i32 [[T10]] to i64
@@ -261,12 +261,11 @@ func instantiate_conditional_conformance_2nd<T>(_ t : T)  where T: Sub, T.S == T
 // CHECK:  [[T14:%.*]] = inttoptr i64 [[T13]] to ptr
 // CHECK-arm64e:  [[T16:%.*]] = ptrtoint ptr [[T14]] to i64
 // CHECK-arm64e:  [[T17:%.*]] = call i64 @llvm.ptrauth.sign(i64 [[T16]], i32 2, i64 47152)
-// CHECK-arm64e:  [[T15:%.*]] = inttoptr i64 [[T17]] to ptr
+// CHECK-arm64e:  [[T14:%.*]] = inttoptr i64 [[T17]] to ptr
 // CHECK:  br label %[[L3:.*]]
 
 // CHECK:[[L3]]:
 // CHECK:  phi ptr [ [[T6]], %[[L1]] ], [ [[T14]], %[[L2]] ]
-// CHECK-arm64e:  phi ptr [ [[T6]], %[[L1]] ], [ [[T15]], %[[L2]] ]
 
 // Passing the witness table.