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Merge pull request #84868 from rjmccall/print-block-ids-nasserts
Add methods to print various SIL things with a SILPrintContext
2 parents 3f7faf0 + 96afc1b commit 70d9add

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6 files changed

+70
-53
lines changed

6 files changed

+70
-53
lines changed

‎include/swift/SIL/SILInstruction.h‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -914,15 +914,17 @@ class SILInstruction : public llvm::ilist_node<SILInstruction> {
914914
/// Pretty-print the value.
915915
void dump() const;
916916
void print(raw_ostream &OS) const;
917+
void print(SILPrintContext &ctx) const;
917918

918919
/// Pretty-print the value with DebugInfo.
919920
void dump(bool DebugInfo) const;
920921

921922
/// Pretty-print the value in context, preceded by its operands (if the
922923
/// value represents the result of an instruction) and followed by its
923924
/// users.
924-
void dumpInContext() const;
925925
void printInContext(raw_ostream &OS) const;
926+
void printInContext(SILPrintContext &ctx) const;
927+
void dumpInContext() const;
926928

927929
static bool classof(SILNodePointer node) {
928930
return node->getKind() >= SILNodeKind::First_SILInstruction &&

‎include/swift/SIL/SILModule.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1145,7 +1145,7 @@ inline llvm::raw_ostream &operator<<(llvm::raw_ostream &OS, const SILModule &M){
11451145
void verificationFailure(const Twine &complaint,
11461146
const SILInstruction *atInstruction,
11471147
const SILArgument *atArgument,
1148-
llvm::function_ref<void(llvm::raw_ostream &OS)> extraContext);
1148+
llvm::function_ref<void(SILPrintContext &ctx)> extraContext);
11491149

11501150
inline bool SILOptions::supportsLexicalLifetimes(const SILModule &mod) const {
11511151
switch (mod.getStage()) {

‎include/swift/SIL/SILNode.h‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -33,6 +33,7 @@ class NonSingleValueInstruction;
3333
class SILModule;
3434
class ValueBase;
3535
class SILNode;
36+
class SILPrintContext;
3637
class SILValue;
3738

3839
/// An enumeration which contains values for all the nodes in SILNodes.def.
@@ -430,12 +431,14 @@ class alignas(8) SILNode :
430431
/// will be valid SIL assembly; otherwise, it will be an arbitrary
431432
/// format suitable for debugging.
432433
void print(raw_ostream &OS) const;
434+
void print(SILPrintContext &ctx) const;
433435
void dump() const;
434436

435437
/// Pretty-print the node in context, preceded by its operands (if the
436438
/// value represents the result of an instruction) and followed by its
437439
/// users.
438440
void printInContext(raw_ostream &OS) const;
441+
void printInContext(SILPrintContext &ctx) const;
439442
void dumpInContext() const;
440443

441444
// Cast to SingleValueInstruction. This is an implementation detail

‎lib/SIL/IR/SILPrinter.cpp‎

Lines changed: 15 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -3372,6 +3372,9 @@ void SILNode::dump() const {
33723372

33733373
void SILNode::print(raw_ostream &OS) const {
33743374
SILPrintContext Ctx(OS);
3375+
print(Ctx);
3376+
}
3377+
void SILNode::print(SILPrintContext &Ctx) const {
33753378
SILPrinter(Ctx).print(this);
33763379
}
33773380

@@ -3391,6 +3394,9 @@ void SingleValueInstruction::dump() const {
33913394

33923395
void SILInstruction::print(raw_ostream &OS) const {
33933396
SILPrintContext Ctx(OS);
3397+
print(Ctx);
3398+
}
3399+
void SILInstruction::print(SILPrintContext &Ctx) const {
33943400
SILPrinter(Ctx).print(this);
33953401
}
33963402

@@ -3413,7 +3419,9 @@ void SILBasicBlock::dump(bool DebugInfo) const {
34133419
/// Pretty-print the SILBasicBlock to the designated stream.
34143420
void SILBasicBlock::print(raw_ostream &OS) const {
34153421
SILPrintContext Ctx(OS);
3416-
3422+
print(Ctx);
3423+
}
3424+
void SILBasicBlock::print(SILPrintContext &Ctx) const {
34173425
// Print the debug scope (and compute if we didn't do it already).
34183426
auto &SM = this->getParent()->getModule().getASTContext().SourceMgr;
34193427
for (auto &I : *this) {
@@ -3424,10 +3432,6 @@ void SILBasicBlock::print(raw_ostream &OS) const {
34243432
SILPrinter(Ctx).print(this);
34253433
}
34263434

3427-
void SILBasicBlock::print(SILPrintContext &Ctx) const {
3428-
SILPrinter(Ctx).print(this);
3429-
}
3430-
34313435
void SILBasicBlock::dumpID(bool newline) const {
34323436
#ifndef NDEBUG
34333437
printID(llvm::errs(), newline);
@@ -4234,6 +4238,9 @@ void SILNode::dumpInContext() const {
42344238
}
42354239
void SILNode::printInContext(llvm::raw_ostream &OS) const {
42364240
SILPrintContext Ctx(OS);
4241+
printInContext(Ctx);
4242+
}
4243+
void SILNode::printInContext(SILPrintContext &Ctx) const {
42374244
SILPrinter(Ctx).printInContext(this);
42384245
}
42394246

@@ -4242,6 +4249,9 @@ void SILInstruction::dumpInContext() const {
42424249
}
42434250
void SILInstruction::printInContext(llvm::raw_ostream &OS) const {
42444251
SILPrintContext Ctx(OS);
4252+
printInContext(Ctx);
4253+
}
4254+
void SILInstruction::printInContext(SILPrintContext &Ctx) const {
42454255
SILPrinter(Ctx).printInContext(asSILNode());
42464256
}
42474257

‎lib/SIL/Utils/BasicBlockUtils.cpp‎

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -615,13 +615,12 @@ static FunctionTest DeadEndEdgesTest("dead_end_edges", [](auto &function,
615615
auto visitingSet = edges.createVisitingSet(/*includeUnreachable*/ true);
616616

617617
auto &out = llvm::outs();
618+
SILPrintContext ctx(out);
618619
for (auto &srcBB : function) {
619620
for (auto *dstBB : srcBB.getSuccessorBlocks()) {
620621
if (auto regionIndex = edges.entersDeadEndRegion(&srcBB, dstBB)) {
621-
srcBB.printID(out, false);
622-
out << " -> ";
623-
dstBB->printID(out, false);
624-
out << " (region " << *regionIndex << "; ";
622+
out << ctx.getID(&srcBB) << " -> " << ctx.getID(dstBB)
623+
<< " (region " << *regionIndex << "; ";
625624
if (visitingSet.visitEdgeTo(dstBB)) {
626625
out << "last edge)";
627626
} else {

‎lib/SIL/Verifier/SILVerifier.cpp‎

Lines changed: 45 additions & 42 deletions
Original file line numberDiff line numberDiff line change
@@ -98,8 +98,9 @@ extern llvm::cl::opt<bool> SILPrintDebugInfo;
9898
void swift::verificationFailure(const Twine &complaint,
9999
const SILInstruction *atInstruction,
100100
const SILArgument *atArgument,
101-
llvm::function_ref<void(llvm::raw_ostream &out)> extraContext) {
101+
llvm::function_ref<void(SILPrintContext &ctx)> extraContext) {
102102
llvm::raw_ostream &out = llvm::dbgs();
103+
SILPrintContext ctx(out);
103104

104105
const SILFunction *f = nullptr;
105106
StringRef funcName = "?";
@@ -116,14 +117,14 @@ void swift::verificationFailure(const Twine &complaint,
116117

117118
out << "SIL verification failed: " << complaint << "\n";
118119
if (extraContext)
119-
extraContext(out);
120+
extraContext(ctx);
120121

121122
if (atInstruction) {
122123
out << "Verifying instruction:\n";
123-
atInstruction->printInContext(out);
124+
atInstruction->printInContext(ctx);
124125
} else if (atArgument) {
125126
out << "Verifying argument:\n";
126-
atArgument->printInContext(out);
127+
atArgument->printInContext(ctx);
127128
}
128129
if (ContinueOnFailure) {
129130
out << "End Error in function " << funcName << "\n";
@@ -978,7 +979,7 @@ class SILVerifier : public SILVerifierBase<SILVerifier> {
978979
}
979980

980981
void _require(bool condition, const Twine &complaint,
981-
llvm::function_ref<void(llvm::raw_ostream &)> extraContext
982+
llvm::function_ref<void(SILPrintContext &)> extraContext
982983
= nullptr) {
983984
if (condition) return;
984985

@@ -1111,16 +1112,16 @@ class SILVerifier : public SILVerifierBase<SILVerifier> {
11111112
/// Assert that two types are equal.
11121113
void requireSameType(Type type1, Type type2, const Twine &complaint) {
11131114
_require(type1->isEqual(type2), complaint,
1114-
[&](llvm::raw_ostream &out) {
1115-
out << " " << type1 << "\n " << type2 << '\n';
1115+
[&](SILPrintContext &ctx) {
1116+
ctx.OS() << " " << type1 << "\n " << type2 << '\n';
11161117
});
11171118
}
11181119

11191120
/// Assert that two types are equal.
11201121
void requireSameType(SILType type1, SILType type2, const Twine &complaint) {
11211122
_require(type1 == type2, complaint,
1122-
[&](llvm::raw_ostream &out) {
1123-
out << " " << type1 << "\n " << type2 << '\n';
1123+
[&](SILPrintContext &ctx) {
1124+
ctx.OS() << " " << type1 << "\n " << type2 << '\n';
11241125
});
11251126
}
11261127

@@ -1158,15 +1159,15 @@ class SILVerifier : public SILVerifierBase<SILVerifier> {
11581159
return;
11591160

11601161
if (!Result.hasPayload()) {
1161-
_require(false, what, [&](llvm::raw_ostream &out) {
1162-
out << " " << Result.getMessage().data() << '\n'
1163-
<< " " << type1 << "\n " << type2 << '\n';
1162+
_require(false, what, [&](SILPrintContext &ctx) {
1163+
ctx.OS() << " " << Result.getMessage().data() << '\n'
1164+
<< " " << type1 << "\n " << type2 << '\n';
11641165
});
11651166
} else {
1166-
_require(false, what, [&](llvm::raw_ostream &out) {
1167-
out << " " << Result.getMessage().data()
1168-
<< ".\nParameter: " << Result.getPayload()
1169-
<< "\n " << type1 << "\n " << type2 << '\n';
1167+
_require(false, what, [&](SILPrintContext &ctx) {
1168+
ctx.OS() << " " << Result.getMessage().data()
1169+
<< ".\nParameter: " << Result.getPayload()
1170+
<< "\n " << type1 << "\n " << type2 << '\n';
11701171
});
11711172
}
11721173
}
@@ -1193,7 +1194,9 @@ class SILVerifier : public SILVerifierBase<SILVerifier> {
11931194
template <class T>
11941195
T *requireValueKind(SILValue value, const Twine &what) {
11951196
auto match = dyn_cast<T>(value);
1196-
_require(match != nullptr, what, [=](llvm::raw_ostream &out) { out << value; });
1197+
_require(match != nullptr, what, [=](SILPrintContext &ctx) {
1198+
value->print(ctx);
1199+
});
11971200
return match;
11981201
}
11991202

@@ -1891,7 +1894,8 @@ class SILVerifier : public SILVerifierBase<SILVerifier> {
18911894
if (subs.getGenericSignature().getCanonicalSignature() !=
18921895
fnTy->getInvocationGenericSignature().getCanonicalSignature()) {
18931896
_require(false, "Substitution map does not match callee in apply instruction",
1894-
[&](llvm::raw_ostream &out) {
1897+
[&](SILPrintContext &ctx) {
1898+
auto &out = ctx.OS();
18951899
out << "substitution map's generic signature: ";
18961900
subs.getGenericSignature()->print(out);
18971901
out << "\n";
@@ -6803,22 +6807,22 @@ class SILVerifier : public SILVerifierBase<SILVerifier> {
68036807
BBState(maybe_movable_ref<BBState> other)
68046808
: BBState(std::move(other).construct()) {}
68056809

6806-
void printStack(llvm::raw_ostream &out, StringRef label) const {
6807-
out << label << ": [";
6808-
if (!Stack.empty()) out << "\n";
6810+
void printStack(SILPrintContext &ctx, StringRef label) const {
6811+
ctx.OS() << label << ": [";
6812+
if (!Stack.empty()) ctx.OS() << "\n";
68096813
for (auto allocation: Stack) {
6810-
allocation->print(out);
6814+
allocation->print(ctx);
68116815
}
6812-
out << "]\n";
6816+
ctx.OS() << "]\n";
68136817
}
68146818

6815-
void printActiveOps(llvm::raw_ostream &out, StringRef label) const {
6816-
out << label << ": [";
6817-
if (!ActiveOps.empty()) out << "\n";
6819+
void printActiveOps(SILPrintContext &ctx, StringRef label) const {
6820+
ctx.OS() << label << ": [";
6821+
if (!ActiveOps.empty()) ctx.OS() << "\n";
68186822
for (auto op: ActiveOps) {
6819-
op->print(out);
6823+
op->print(ctx);
68206824
}
6821-
out << "]\n";
6825+
ctx.OS() << "]\n";
68226826
}
68236827

68246828
/// Given that we have two edges to the same block or dead-end region,
@@ -6877,14 +6881,13 @@ class SILVerifier : public SILVerifierBase<SILVerifier> {
68776881
// conservative merge regardless of failure so that we're in a
68786882
// coherent state in the successor block.
68796883
auto fail = [&](StringRef complaint,
6880-
llvm::function_ref<void(llvm::raw_ostream &out)> extra
6884+
llvm::function_ref<void(SILPrintContext &out)> extra
68816885
= nullptr) {
68826886
verificationFailure(complaint, term, nullptr,
6883-
[&](llvm::raw_ostream &out) {
6884-
out << "Entering basic block ";
6885-
succBB->printID(out, /*newline*/ true);
6887+
[&](SILPrintContext &ctx) {
6888+
ctx.OS() << "Entering basic block " << ctx.getID(succBB) << "\n";
68866889

6887-
if (extra) extra(out);
6890+
if (extra) extra(ctx);
68886891
});
68896892
};
68906893

@@ -6908,9 +6911,9 @@ class SILVerifier : public SILVerifierBase<SILVerifier> {
69086911
if (Stack != otherState.Stack) {
69096912
if (!isDeadEndEdge) {
69106913
fail("inconsistent stack states entering basic block",
6911-
[&](llvm::raw_ostream &out) {
6912-
otherState.printStack(out, "Current stack state");
6913-
printStack(out, "Recorded stack state");
6914+
[&](SILPrintContext &ctx) {
6915+
otherState.printStack(ctx, "Current stack state");
6916+
printStack(ctx, "Recorded stack state");
69146917
});
69156918
}
69166919

@@ -6923,9 +6926,9 @@ class SILVerifier : public SILVerifierBase<SILVerifier> {
69236926
if (ActiveOps != otherState.ActiveOps) {
69246927
if (!isDeadEndEdge) {
69256928
fail("inconsistent active-operations sets entering basic block",
6926-
[&](llvm::raw_ostream &out) {
6927-
otherState.printActiveOps(out, "Current active operations");
6928-
printActiveOps(out, "Recorded active operations");
6929+
[&](SILPrintContext &ctx) {
6930+
otherState.printActiveOps(ctx, "Current active operations");
6931+
printActiveOps(ctx, "Recorded active operations");
69296932
});
69306933
}
69316934

@@ -7021,9 +7024,9 @@ class SILVerifier : public SILVerifierBase<SILVerifier> {
70217024
} else {
70227025
verificationFailure("deallocating allocation that is not the top of the stack",
70237026
&i, nullptr,
7024-
[&](llvm::raw_ostream &out) {
7025-
state.printStack(out, "Current stack state");
7026-
out << "Stack allocation:\n" << *op;
7027+
[&](SILPrintContext &ctx) {
7028+
state.printStack(ctx, "Current stack state");
7029+
ctx.OS() << "Stack allocation:\n" << *op;
70277030
// The deallocation is printed out as the focus of the failure.
70287031
});
70297032
}

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