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Merge pull request #83901 from meg-gupta/printsilmodule
Add options to print the SIL module after SILGen and SIL passes
2 parents 0038b92 + 3ef1040 commit 745bef6

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lib/SILOptimizer/PassManager/PassPipeline.cpp

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@@ -62,6 +62,14 @@ static llvm::cl::opt<bool> SILViewSILGenCFG(
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"sil-view-silgen-cfg", llvm::cl::init(false),
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llvm::cl::desc("Enable the sil cfg viewer pass before diagnostics"));
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static llvm::cl::opt<bool> SILPrintSILGenModule(
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"sil-print-silgen-module", llvm::cl::init(false),
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llvm::cl::desc("Enable printing the module after SILGen"));
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static llvm::cl::opt<bool> SILPrintFinalModule(
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"sil-print-final-module", llvm::cl::init(false),
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llvm::cl::desc("Enable printing the module after all SIL passes"));
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//===----------------------------------------------------------------------===//
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// Diagnostic Pass Pipeline
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//===----------------------------------------------------------------------===//
@@ -283,6 +291,9 @@ SILPassPipelinePlan::getSILGenPassPipeline(const SILOptions &Options) {
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if (SILViewSILGenCFG) {
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addCFGPrinterPipeline(P, "SIL View SILGen CFG");
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}
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if (SILPrintSILGenModule) {
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addModulePrinterPipeline(P, "SIL Print SILGen Module");
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}
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return P;
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}
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@@ -1044,6 +1055,9 @@ SILPassPipelinePlan::getPerformancePassPipeline(const SILOptions &Options) {
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if (SILViewCFG) {
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addCFGPrinterPipeline(P, "SIL Before IRGen View CFG");
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}
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if (SILPrintFinalModule) {
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addModulePrinterPipeline(P, "SIL Print Final Module");
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}
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return P;
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}
@@ -1127,6 +1141,9 @@ SILPassPipelinePlan::getOnonePassPipeline(const SILOptions &Options) {
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// Has only an effect if the -sil-based-debuginfo option is specified.
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P.addSILDebugInfoGenerator();
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if (SILPrintFinalModule) {
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addModulePrinterPipeline(P, "SIL Print Final Module");
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}
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return P;
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}
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