The instance alignment mask in the class metadata is a 16-bit field, and must be loaded with a 16-bit load instruction for correctness on big-endian systems.

Author: bryanpkc

lib/IRGen/GenMeta.cpp

@@ -4338,16 +4338,20 @@ irgen::emitClassResilientInstanceSizeAndAlignMask(IRGenFunction &IGF,
          && "didn't find size or alignment in metadata?!");
   Address metadataAsBytes(IGF.Builder.CreateBitCast(metadata, IGF.IGM.Int8PtrTy),
                           IGF.IGM.getPointerAlignment());
-  auto loadZExtInt32AtOffset = [&](Size offset) {
-    Address slot = IGF.Builder.CreateConstByteArrayGEP(metadataAsBytes, offset);
-    slot = IGF.Builder.CreateBitCast(slot, IGF.IGM.Int32Ty->getPointerTo());
-    llvm::Value *result = IGF.Builder.CreateLoad(slot);
-    if (IGF.IGM.SizeTy != IGF.IGM.Int32Ty)
-      result = IGF.Builder.CreateZExt(result, IGF.IGM.SizeTy);
-    return result;
-  };
-  llvm::Value *size = loadZExtInt32AtOffset(scanner.InstanceSize);
-  llvm::Value *alignMask = loadZExtInt32AtOffset(scanner.InstanceAlignMask);
+
+  Address slot = IGF.Builder.CreateConstByteArrayGEP(metadataAsBytes,
+                                                     scanner.InstanceSize);
+  slot = IGF.Builder.CreateBitCast(slot, IGF.IGM.Int32Ty->getPointerTo());
+  llvm::Value *size = IGF.Builder.CreateLoad(slot);
+  if (IGF.IGM.SizeTy != IGF.IGM.Int32Ty)
+    size = IGF.Builder.CreateZExt(size, IGF.IGM.SizeTy);
+
+  slot = IGF.Builder.CreateConstByteArrayGEP(metadataAsBytes,
+                                             scanner.InstanceAlignMask);
+  slot = IGF.Builder.CreateBitCast(slot, IGF.IGM.Int16Ty->getPointerTo());
+  llvm::Value *alignMask = IGF.Builder.CreateLoad(slot);
+  alignMask = IGF.Builder.CreateZExt(alignMask, IGF.IGM.SizeTy);
+
   return {size, alignMask};
 }
 

test/IRGen/class.sil

@@ -97,9 +97,9 @@ bb0(%0 : $@thick C.Type):
   // CHECK:   [[SIZE32:%.*]] = load i32, i32* [[T1]], align 8
   // CHECK:   [[SIZE:%.*]] = zext i32 [[SIZE32]] to i64
   // CHECK:   [[T0:%.*]] = getelementptr inbounds i8, i8* [[META_PTR]], i32 52
-  // CHECK:   [[T1:%.*]] = bitcast i8* [[T0]] to i32*
-  // CHECK:   [[ALIGN32:%.*]] = load i32, i32* [[T1]], align 4
-  // CHECK:   [[ALIGN:%.*]] = zext i32 [[ALIGN32]] to i64
+  // CHECK:   [[T1:%.*]] = bitcast i8* [[T0]] to i16*
+  // CHECK:   [[ALIGN16:%.*]] = load i16, i16* [[T1]], align 4
+  // CHECK:   [[ALIGN:%.*]] = zext i16 [[ALIGN16]] to i64
   // CHECK:   [[RESULT:%[0-9]+]] = call noalias %swift.refcounted* @rt_swift_allocObject(%swift.type* %0, i64 [[SIZE]], i64 [[ALIGN]])
   %1 = alloc_ref_dynamic %0 : $@thick C.Type, $C
   return %1 : $C

test/IRGen/generic_classes.sil

@@ -211,9 +211,9 @@ sil @_TFC15generic_classes31RecursiveGenericInheritsGenericD : $@convention(meth
 // CHECK:   [[SIZE32:%.*]] = load i32, i32* [[T1]], align 8
 // CHECK:   [[SIZE:%.*]] = zext i32 [[SIZE32]] to i64
 // CHECK:   [[T0:%.*]] = getelementptr inbounds i8, i8* [[METADATA_ARRAY]], i32 52
-// CHECK:   [[T1:%.*]] = bitcast i8* [[T0]] to i32*
-// CHECK:   [[ALIGN32:%.*]] = load i32, i32* [[T1]], align 4
-// CHECK:   [[ALIGN:%.*]] = zext i32 [[ALIGN32]] to i64
+// CHECK:   [[T1:%.*]] = bitcast i8* [[T0]] to i16*
+// CHECK:   [[ALIGN16:%.*]] = load i16, i16* [[T1]], align 4
+// CHECK:   [[ALIGN:%.*]] = zext i16 [[ALIGN16]] to i64
 // CHECK:   call noalias %swift.refcounted* @rt_swift_allocObject(%swift.type* [[METADATA]], i64 [[SIZE]], i64 [[ALIGN]])
 sil @RootGeneric_fragile_dependent_alloc : $<G> () -> RootGeneric<G> {
 entry: