Skip to content

Commit aac670d

Browse files
kateinoigakukunkateinoigakukun
committed
Pretty-print more instructions
1 parent 79aaf6e commit aac670d

File tree

2 files changed

+59
-28
lines changed

2 files changed

+59
-28
lines changed

‎Sources/WasmKit/Execution/Instructions/InstructionSupport.swift‎

Lines changed: 58 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -256,6 +256,11 @@ struct InstructionPrintingContext {
256256
"offset: \(offset)"
257257
}
258258

259+
func branchTarget(_ instructionOffset: Int, _ offset: Int) -> String {
260+
let iseqOffset = instructionOffset + offset
261+
return "\(offset > 0 ? "+" : "")\(offset) ; 0x\(String(iseqOffset, radix: 16))"
262+
}
263+
259264
mutating func callee(_ callee: InternalFunction) -> String {
260265
return "'" + nameRegistry.symbolicate(callee) + "'"
261266
}
@@ -278,11 +283,25 @@ struct InstructionPrintingContext {
278283
instructionOffset: Int,
279284
to target: inout Target
280285
) where Target: TextOutputStream {
286+
func binop(_ name: String, _ op: Instruction.BinaryOperand) {
287+
target.write("\(reg(op.result)) = \(name) \(reg(op.lhs)), \(reg(op.rhs))")
288+
}
289+
func unop(_ name: String, _ op: Instruction.UnaryOperand) {
290+
target.write("\(reg(op.result)) = \(name) \(reg(op.input))")
291+
}
292+
func load(_ name: String, _ op: Instruction.LoadOperand) {
293+
target.write("\(reg(op.result)) = \(name) \(reg(op.pointer)), \(offset(op.offset))")
294+
}
295+
func store(_ name: String, _ op: Instruction.StoreOperand) {
296+
target.write("\(name) \(reg(op.pointer)) + \(offset(op.offset)), \(reg(op.value))")
297+
}
281298
switch instruction {
282299
case .unreachable:
283300
target.write("unreachable")
284301
case .nop:
285302
target.write("nop")
303+
case .copyStack(let op):
304+
target.write("\(reg(op.dest)) = copy \(reg(op.source))")
286305
case .globalGet(let op):
287306
target.write("\(reg(op.reg)) = global.get \(global(op.global))")
288307
case .globalSet(let op):
@@ -295,39 +314,51 @@ struct InstructionPrintingContext {
295314
target.write("call_indirect \(reg(op.index)), \(op.tableIndex), (func_ty id:\(op.type.id)), sp: +\(op.spAddend)")
296315
case .compilingCall(let op):
297316
target.write("compiling_call \(callee(op.callee)), sp: +\(op.spAddend)")
298-
case .i32Load(let op):
299-
target.write("\(reg(op.result)) = i32.load \(reg(op.pointer)), \(offset(op.offset))")
300-
case .i64Load(let op):
301-
target.write("\(reg(op.result)) = i64.load \(reg(op.pointer)), \(offset(op.offset))")
302-
case .f32Load(let op):
303-
target.write("\(reg(op.result)) = f32.load \(reg(op.pointer)), \(offset(op.offset))")
304-
case .f64Load(let op):
305-
target.write("\(reg(op.result)) = f64.load \(reg(op.pointer)), \(offset(op.offset))")
306-
case .copyStack(let op):
307-
target.write("\(reg(op.dest)) = copy \(reg(op.source))")
308-
case .i32Add(let op):
309-
target.write("\(reg(op.result)) = i32.add \(reg(op.lhs)), \(reg(op.rhs))")
310-
case .i32Sub(let op):
311-
target.write("\(reg(op.result)) = i32.sub \(reg(op.lhs)), \(reg(op.rhs))")
312-
case .i32LtU(let op):
313-
target.write("\(reg(op.result)) = i32.lt_u \(reg(op.lhs)), \(reg(op.rhs))")
314-
case .i32Eq(let op):
315-
target.write("\(reg(op.result)) = i32.eq \(reg(op.lhs)), \(reg(op.rhs))")
316-
case .i32Eqz(let op):
317-
target.write("\(reg(op.result)) = i32.eqz \(reg(op.input))")
318-
case .i32Store(let op):
319-
target.write("i32.store \(reg(op.pointer)), \(reg(op.value)), \(offset(op.offset))")
317+
case .i32Load(let op): load("i32.load", op)
318+
case .i64Load(let op): load("i64.load", op)
319+
case .f32Load(let op): load("f32.load", op)
320+
case .f64Load(let op): load("f64.load", op)
321+
case .i32Add(let op): binop("i32.add", op)
322+
case .i32Sub(let op): binop("i32.sub", op)
323+
case .i32Mul(let op): binop("i32.mul", op)
324+
case .i32DivS(let op): binop("i32.div_s", op)
325+
case .i32RemS(let op): binop("i32.rem_s", op)
326+
case .i32And(let op): binop("i32.and", op)
327+
case .i32Or(let op): binop("i32.or", op)
328+
case .i32Xor(let op): binop("i32.xor", op)
329+
case .i32Shl(let op): binop("i32.shl", op)
330+
case .i32ShrS(let op): binop("i32.shr_s", op)
331+
case .i32ShrU(let op): binop("i32.shr_u", op)
332+
case .i32Rotl(let op): binop("i32.rotl", op)
333+
case .i32Rotr(let op): binop("i32.rotr", op)
334+
case .i32LtU(let op): binop("i32.lt_u", op)
335+
case .i32GeU(let op): binop("i32.ge_u", op)
336+
case .i32Eq(let op): binop("i32.eq", op)
337+
case .i32Eqz(let op): unop("i32.eqz", op)
338+
case .i64Add(let op): binop("i64.add", op)
339+
case .i64Sub(let op): binop("i64.sub", op)
340+
case .i64Mul(let op): binop("i64.mul", op)
341+
case .i64DivS(let op): binop("i64.div_s", op)
342+
case .i64RemS(let op): binop("i64.rem_s", op)
343+
case .i64And(let op): binop("i64.and", op)
344+
case .i64Or(let op): binop("i64.or", op)
345+
case .i64Xor(let op): binop("i64.xor", op)
346+
case .i64Shl(let op): binop("i64.shl", op)
347+
case .i64ShrS(let op): binop("i64.shr_s", op)
348+
case .i64ShrU(let op): binop("i64.shr_u", op)
349+
case .i64Eq(let op): binop("i64.eq", op)
350+
case .i64Eqz(let op): unop("i64.eqz", op)
351+
case .i32Store(let op): store("i32.store", op)
320352
case .brIfNot(let op):
321-
target.write("br_if_not \(reg(op.condition)), +\(op.offset)")
353+
target.write("br_if_not \(reg(op.condition)), \(branchTarget(instructionOffset, Int(op.offset)))")
322354
case .brIf(let op):
323-
target.write("br_if \(reg(op.condition)), +\(op.offset)")
355+
target.write("br_if \(reg(op.condition)), \(branchTarget(instructionOffset, Int(op.offset)))")
324356
case .br(let offset):
325-
let iseqOffset = instructionOffset + Int(offset)
326-
target.write("br \(offset > 0 ? "+" : "")\(offset) ; 0x\(String(iseqOffset, radix: 16))")
357+
target.write("br \(branchTarget(instructionOffset, Int(offset)))")
327358
case .brTable(let table):
328359
target.write("br_table \(reg(table.index)), \(table.count) cases")
329360
for i in 0..<table.count {
330-
target.write("\n \(i): +\(table.baseAddress[Int(i)].offset)")
361+
target.write("\n \(i): \(branchTarget(instructionOffset, Int(table.baseAddress[Int(i)].offset)) )")
331362
}
332363
case ._return:
333364
target.write("return")

‎Sources/WasmKit/Execution/NameRegistry.swift‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -48,7 +48,7 @@ struct NameRegistry {
4848
}
4949
// Fallback
5050
if function.isWasm {
51-
return "unknown function[\(function.wasm.index)]"
51+
return "function[\(function.wasm.index)]"
5252
} else {
5353
return "unknown host function"
5454
}

0 commit comments

Comments
 (0)