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Fix shifted register printing
1 parent 15e3396 commit e0e3823

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+11
-4
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+11
-4
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Sources/WasmKit/Execution/Instructions/InstructionSupport.swift

Lines changed: 11 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,7 @@ protocol ShiftedVReg {
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/// A larger (32-bit) version of `VReg`
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/// Used to utilize halfword loads instructions.
17-
struct LVReg: Equatable, ShiftedVReg {
17+
struct LVReg: Equatable, ShiftedVReg, CustomStringConvertible {
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let value: Int32
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init(_ value: VReg) {
@@ -26,11 +26,15 @@ struct LVReg: Equatable, ShiftedVReg {
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init(storage: Int32) {
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self.value = storage
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}
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var description: String {
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"\(value / Int32(MemoryLayout<StackSlot>.size))"
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}
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}
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/// A larger (64-bit) version of `VReg`
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/// Used to utilize word loads instructions.
33-
struct LLVReg: Equatable, ShiftedVReg {
37+
struct LLVReg: Equatable, ShiftedVReg, CustomStringConvertible {
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let value: Int64
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init(_ value: VReg) {
@@ -42,6 +46,10 @@ struct LLVReg: Equatable, ShiftedVReg {
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init(storage: Int64) {
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self.value = storage
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}
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var description: String {
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"\(value / Int64(MemoryLayout<StackSlot>.size))"
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}
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}
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// MARK: - Immediate load/emit support
@@ -238,8 +246,7 @@ struct InstructionPrintingContext {
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return "reg:\(reg)"
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}
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}
241-
func reg(_ x: LVReg) -> String { reg(x.value) }
242-
func reg(_ x: LLVReg) -> String { reg(x.value) }
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func reg<R: ShiftedVReg>(_ x: R) -> String { reg(Int(x.value) / MemoryLayout<StackSlot>.size) }
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func offset(_ offset: UInt64) -> String {
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"offset: \(offset)"

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