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Merge pull request swiftlang#18717 from adrian-prantl/43296089
Add initial support for debug info for coroutine allocas.
2 parents d2e1a0d + 556c8e5 commit cbd53a0

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2 files changed

+22
-10
lines changed

2 files changed

+22
-10
lines changed

lib/IRGen/IRGenDebugInfo.cpp

Lines changed: 11 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -2003,21 +2003,25 @@ void IRGenDebugInfoImpl::emitDbgIntrinsic(
20032003
return;
20042004

20052005
// A dbg.declare is only meaningful if there is a single alloca for
2006-
// the variable that is live throughout the function. With SIL
2007-
// optimizations this is not guaranteed and a variable can end up in
2008-
// two allocas (for example, one function inlined twice).
2006+
// the variable that is live throughout the function.
20092007
if (auto *Alloca = dyn_cast<llvm::AllocaInst>(Storage)) {
20102008
auto *ParentBB = Alloca->getParent();
20112009
auto InsertBefore = std::next(Alloca->getIterator());
20122010
if (InsertBefore != ParentBB->end())
20132011
DBuilder.insertDeclare(Alloca, Var, Expr, DL, &*InsertBefore);
20142012
else
20152013
DBuilder.insertDeclare(Alloca, Var, Expr, DL, ParentBB);
2016-
return;
2014+
} else if (isa<llvm::IntrinsicInst>(Storage) &&
2015+
cast<llvm::IntrinsicInst>(Storage)->getIntrinsicID() ==
2016+
llvm::Intrinsic::coro_alloca_get) {
2017+
// FIXME: The live range of a coroutine alloca within the function may be
2018+
// limited, so using a dbg.addr instead of a dbg.declare would be more
2019+
// appropriate.
2020+
DBuilder.insertDeclare(Storage, Var, Expr, DL, BB);
2021+
} else {
2022+
// Insert a dbg.value at the current insertion point.
2023+
DBuilder.insertDbgValueIntrinsic(Storage, Var, Expr, DL, BB);
20172024
}
2018-
2019-
// Insert a dbg.value at the current insertion point.
2020-
DBuilder.insertDbgValueIntrinsic(Storage, Var, Expr, DL, BB);
20212025
}
20222026

20232027
void IRGenDebugInfoImpl::emitGlobalVariableDeclaration(

lib/IRGen/IRGenSIL.cpp

Lines changed: 11 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -4001,9 +4001,15 @@ void IRGenSILFunction::emitDebugInfoForAllocStack(AllocStackInst *i,
40014001
VarDecl *Decl = i->getDecl();
40024002
// Describe the underlying alloca. This way an llvm.dbg.declare instrinsic
40034003
// is used, which is valid for the entire lifetime of the alloca.
4004-
if (auto *BitCast = dyn_cast<llvm::BitCastInst>(addr))
4005-
if (auto *Alloca = dyn_cast<llvm::AllocaInst>(BitCast->getOperand(0)))
4004+
if (auto *BitCast = dyn_cast<llvm::BitCastInst>(addr)) {
4005+
auto *Op0 = BitCast->getOperand(0);
4006+
if (auto *Alloca = dyn_cast<llvm::AllocaInst>(Op0))
40064007
addr = Alloca;
4008+
else if (auto *CoroAllocaGet = dyn_cast<llvm::IntrinsicInst>(Op0)) {
4009+
if (CoroAllocaGet->getIntrinsicID() == llvm::Intrinsic::coro_alloca_get)
4010+
addr = CoroAllocaGet;
4011+
}
4012+
}
40074013

40084014
auto DS = i->getDebugScope();
40094015
if (!DS)
@@ -4016,7 +4022,9 @@ void IRGenSILFunction::emitDebugInfoForAllocStack(AllocStackInst *i,
40164022
StringRef Name = getVarName(i, IsAnonymous);
40174023

40184024
// At this point addr must be an alloca or an undef.
4019-
assert(isa<llvm::AllocaInst>(addr) || isa<llvm::UndefValue>(addr));
4025+
assert(isa<llvm::AllocaInst>(addr) || isa<llvm::UndefValue>(addr) ||
4026+
isa<llvm::IntrinsicInst>(addr));
4027+
40204028
auto Indirection = DirectValue;
40214029
if (!IGM.IRGen.Opts.shouldOptimize())
40224030
if (auto *Alloca = dyn_cast<llvm::AllocaInst>(addr))

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