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eecksteineeckstein
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Merge pull request swiftlang#68699 from eeckstein/fix-disable-llvm-optzns
IRGen: fix -disable-llvm-optzns
2 parents 1cd423d + b5de7e4 commit ebc0be2

12 files changed

+24
-17
lines changed

‎lib/IRGen/IRGen.cpp‎

Lines changed: 4 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -369,8 +369,6 @@ void swift::performLLVMOptimizations(const IRGenOptions &Opts,
369369
MPM.addPass(InlineTreePrinterPass());
370370

371371
// Add bitcode/ll output passes to pass manager.
372-
ModulePassManager EmptyPassManager;
373-
auto &PassManagerToRun = Opts.DisableLLVMOptzns ? EmptyPassManager : MPM;
374372

375373
switch (Opts.OutputKind) {
376374
case IRGenOutputKind::LLVMAssemblyBeforeOptimization:
@@ -380,7 +378,7 @@ void swift::performLLVMOptimizations(const IRGenOptions &Opts,
380378
case IRGenOutputKind::Module:
381379
break;
382380
case IRGenOutputKind::LLVMAssemblyAfterOptimization:
383-
PassManagerToRun.addPass(PrintModulePass(*out, "", false));
381+
MPM.addPass(PrintModulePass(*out, "", false));
384382
break;
385383
case IRGenOutputKind::LLVMBitcode: {
386384
// Emit a module summary by default for Regular LTO except ld64-based ones
@@ -389,7 +387,7 @@ void swift::performLLVMOptimizations(const IRGenOptions &Opts,
389387
TargetMachine->getTargetTriple().getVendor() != llvm::Triple::Apple;
390388

391389
if (Opts.LLVMLTOKind == IRGenLLVMLTOKind::Thin) {
392-
PassManagerToRun.addPass(ThinLTOBitcodeWriterPass(*out, nullptr));
390+
MPM.addPass(ThinLTOBitcodeWriterPass(*out, nullptr));
393391
} else {
394392
if (EmitRegularLTOSummary) {
395393
Module->addModuleFlag(llvm::Module::Error, "ThinLTO", uint32_t(0));
@@ -399,14 +397,14 @@ void swift::performLLVMOptimizations(const IRGenOptions &Opts,
399397
Module->addModuleFlag(llvm::Module::Error, "EnableSplitLTOUnit",
400398
uint32_t(1));
401399
}
402-
PassManagerToRun.addPass(BitcodeWriterPass(
400+
MPM.addPass(BitcodeWriterPass(
403401
*out, /*ShouldPreserveUseListOrder*/ false, EmitRegularLTOSummary));
404402
}
405403
break;
406404
}
407405
}
408406

409-
PassManagerToRun.run(*Module, MAM);
407+
MPM.run(*Module, MAM);
410408

411409
if (AlignModuleToPageSize) {
412410
align(Module);

‎test/IRGen/async/get_async_continuation.sil‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
// RUN: %target-swift-frontend -g -enable-objc-interop -primary-file %s -emit-ir -sil-verify-all -disable-llvm-optzns -disable-swift-specific-llvm-optzns | %IRGenFileCheck %s
1+
// RUN: %target-swift-frontend -g -enable-objc-interop -primary-file %s -emit-irgen -sil-verify-all | %IRGenFileCheck %s
22
// RUN: %target-swift-frontend -enable-objc-interop -primary-file %s -emit-ir -sil-verify-all
33

44
// REQUIRES: concurrency

‎test/IRGen/async/hop_to_executor.sil‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
// RUN: %target-swift-frontend -primary-file %s -module-name=test -disable-llvm-optzns -disable-swift-specific-llvm-optzns -emit-ir -sil-verify-all | %IRGenFileCheck %s -check-prefix CHECK-%target-abi
1+
// RUN: %target-swift-frontend -primary-file %s -module-name=test -emit-irgen -sil-verify-all | %IRGenFileCheck %s -check-prefix CHECK-%target-abi
22

33
// REQUIRES: concurrency
44

‎test/IRGen/async/unreachable.swift‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
// RUN: %target-swift-frontend -primary-file %s -g -emit-ir -disable-availability-checking -disable-llvm-optzns -disable-swift-specific-llvm-optzns | %FileCheck %s
1+
// RUN: %target-swift-frontend -primary-file %s -g -emit-irgen -disable-availability-checking | %FileCheck %s
22
// REQUIRES: concurrency
33

44
// CHECK: call i1 (ptr, i1, ...) @llvm.coro.end.async

‎test/IRGen/clang_inline.swift‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,10 @@
11
// RUN: %empty-directory(%t)
22
// RUN: %build-irgen-test-overlays
3-
// RUN: %target-swift-frontend -enable-objc-interop -sdk %S/Inputs -primary-file %s -O -disable-sil-perf-optzns -disable-llvm-optzns -emit-ir -Xcc -fstack-protector -I %t | %FileCheck %s
3+
// RUN: %target-swift-frontend -enable-objc-interop -sdk %S/Inputs -primary-file %s -O -disable-sil-perf-optzns -emit-irgen -Xcc -fstack-protector -I %t | %FileCheck %s
44

55
// RUN: %empty-directory(%t/Empty.framework/Modules/Empty.swiftmodule)
66
// RUN: %target-swift-frontend -emit-module-path %t/Empty.framework/Modules/Empty.swiftmodule/%target-swiftmodule-name %S/../Inputs/empty.swift -module-name Empty -I %t
7-
// RUN: %target-swift-frontend -sdk %S/Inputs -primary-file %s -I %t -F %t -DIMPORT_EMPTY -O -disable-sil-perf-optzns -disable-llvm-optzns -emit-ir -Xcc -fstack-protector -enable-objc-interop | %FileCheck %s
7+
// RUN: %target-swift-frontend -sdk %S/Inputs -primary-file %s -I %t -F %t -DIMPORT_EMPTY -O -disable-sil-perf-optzns -emit-irgen -Xcc -fstack-protector -enable-objc-interop | %FileCheck %s
88

99
// REQUIRES: CPU=i386 || CPU=x86_64
1010
// REQUIRES: objc_interop

‎test/IRGen/debug_fragment_merge.swift‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
// RUN: %target-swift-frontend -disable-availability-checking -primary-file %s -emit-sil -O -g | %FileCheck %s --check-prefix CHECK-SIL
2-
// RUN: %target-swift-frontend -disable-availability-checking -primary-file %s -emit-ir -disable-llvm-optzns -O -g | %FileCheck %s
2+
// RUN: %target-swift-frontend -disable-availability-checking -primary-file %s -emit-irgen -O -g | %FileCheck %s
33

44
// REQUIRES: CPU=arm64 || CPU=x86_64 || CPU=arm64e
55

‎test/IRGen/disable-llvm-optzns.swift‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,9 @@
1+
// RUN: %target-swift-frontend -primary-file %s -disable-availability-checking -c -o /dev/null -O -disable-llvm-optzns
2+
3+
// REQUIRES: concurrency
4+
5+
// Check that -disable-llvm-optzns does not crash the compiler
6+
7+
func testit() async {
8+
print(1)
9+
}

‎test/IRGen/modifyaccessor.swift‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
// RUN: %target-swift-frontend -emit-ir -disable-llvm-optzns -disable-swift-specific-llvm-optzns -primary-file %s | %FileCheck %s
1+
// RUN: %target-swift-frontend -emit-irgen -primary-file %s | %FileCheck %s
22
extension Dictionary {
33
subscript(alternate key: Key) -> Value? {
44
get {

‎test/IRGen/yield_once.sil‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
// RUN: %target-swift-frontend -emit-ir -disable-llvm-optzns -disable-swift-specific-llvm-optzns %s | %FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-%target-ptrsize --check-prefix=CHECK-%target-ptrsize-%target-ptrauth
1+
// RUN: %target-swift-frontend -emit-irgen %s | %FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-%target-ptrsize --check-prefix=CHECK-%target-ptrsize-%target-ptrauth
22

33
import Builtin
44

‎test/IRGen/yield_once_big.sil‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
// RUN: %target-swift-frontend -emit-ir -disable-llvm-optzns -disable-swift-specific-llvm-optzns %s | %FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-%target-ptrsize --check-prefix=CHECK-%target-ptrsize-%target-ptrauth -DINT=i%target-ptrsize
1+
// RUN: %target-swift-frontend -emit-irgen %s | %FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-%target-ptrsize --check-prefix=CHECK-%target-ptrsize-%target-ptrauth -DINT=i%target-ptrsize
22
// UNSUPPORTED: CPU=arm64_32
33

44
import Builtin

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