AMDGPU: Fold mov imm to copy to av_32 class (llvm#155428)

Previously we had special case folding into copies to AGPR_32,
ignoring AV_32. Try folding into the pseudos.

Not sure why the true16 case regressed.

Author: arsenm

llvm/lib/Target/AMDGPU/SIFoldOperands.cpp

@@ -1260,17 +1260,6 @@ void SIFoldOperandsImpl::foldOperand(
       return;
 
     const TargetRegisterClass *DestRC = TRI->getRegClassForReg(*MRI, DestReg);
-    if (!DestReg.isPhysical() && DestRC == &AMDGPU::AGPR_32RegClass) {
-      std::optional<int64_t> UseImmVal = OpToFold.getEffectiveImmVal();
-      if (UseImmVal && TII->isInlineConstant(
-                           *UseImmVal, AMDGPU::OPERAND_REG_INLINE_C_INT32)) {
-        UseMI->setDesc(TII->get(AMDGPU::V_ACCVGPR_WRITE_B32_e64));
-        UseMI->getOperand(1).ChangeToImmediate(*UseImmVal);
-        CopiesToReplace.push_back(UseMI);
-        return;
-      }
-    }
-
     // Allow immediates COPYd into sgpr_lo16 to be further folded while
     // still being legal if not further folded
     if (DestRC == &AMDGPU::SGPR_LO16RegClass) {
@@ -1283,7 +1272,8 @@ void SIFoldOperandsImpl::foldOperand(
     // MOV. Find a compatible mov instruction with the value.
     for (unsigned MovOp :
          {AMDGPU::S_MOV_B32, AMDGPU::V_MOV_B32_e32, AMDGPU::S_MOV_B64,
-          AMDGPU::V_MOV_B64_PSEUDO, AMDGPU::V_MOV_B16_t16_e64}) {
+          AMDGPU::V_MOV_B64_PSEUDO, AMDGPU::V_MOV_B16_t16_e64,
+          AMDGPU::V_ACCVGPR_WRITE_B32_e64, AMDGPU::AV_MOV_B32_IMM_PSEUDO}) {
       const MCInstrDesc &MovDesc = TII->get(MovOp);
       assert(MovDesc.getNumDefs() > 0 && MovDesc.operands()[0].RegClass != -1);
 

llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior2.ll

@@ -166,14 +166,13 @@ define amdgpu_kernel void @with_private_to_flat_addrspacecast_cc_kernel(ptr addr
 ; GFX942-ARCH-FLAT:       ; %bb.0:
 ; GFX942-ARCH-FLAT-NEXT:    s_load_dword s2, s[4:5], 0x0
 ; GFX942-ARCH-FLAT-NEXT:    s_mov_b64 s[0:1], src_private_base
-; GFX942-ARCH-FLAT-NEXT:    s_mov_b32 s0, 0
-; GFX942-ARCH-FLAT-NEXT:    v_mov_b32_e32 v2, s0
+; GFX942-ARCH-FLAT-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX942-ARCH-FLAT-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX942-ARCH-FLAT-NEXT:    s_cmp_lg_u32 s2, -1
-; GFX942-ARCH-FLAT-NEXT:    s_cselect_b32 s1, s1, 0
-; GFX942-ARCH-FLAT-NEXT:    s_cselect_b32 s2, s2, 0
-; GFX942-ARCH-FLAT-NEXT:    v_mov_b32_e32 v0, s2
-; GFX942-ARCH-FLAT-NEXT:    v_mov_b32_e32 v1, s1
+; GFX942-ARCH-FLAT-NEXT:    s_cselect_b32 s0, s1, 0
+; GFX942-ARCH-FLAT-NEXT:    s_cselect_b32 s1, s2, 0
+; GFX942-ARCH-FLAT-NEXT:    v_mov_b32_e32 v0, s1
+; GFX942-ARCH-FLAT-NEXT:    v_mov_b32_e32 v1, s0
 ; GFX942-ARCH-FLAT-NEXT:    flat_store_dword v[0:1], v2 sc0 sc1
 ; GFX942-ARCH-FLAT-NEXT:    s_waitcnt vmcnt(0)
 ; GFX942-ARCH-FLAT-NEXT:    s_endpgm

llvm/test/CodeGen/AMDGPU/flat-scratch.ll

@@ -463,8 +463,7 @@ define amdgpu_kernel void @store_load_sindex_kernel(i32 %idx) {
 ; GFX942-LABEL: store_load_sindex_kernel:
 ; GFX942:       ; %bb.0: ; %bb
 ; GFX942-NEXT:    s_load_dword s0, s[4:5], 0x24
-; GFX942-NEXT:    s_mov_b32 s1, 15
-; GFX942-NEXT:    v_mov_b32_e32 v0, s1
+; GFX942-NEXT:    v_mov_b32_e32 v0, 15
 ; GFX942-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX942-NEXT:    s_lshl_b32 s1, s0, 2
 ; GFX942-NEXT:    s_and_b32 s0, s0, 15
@@ -611,9 +610,8 @@ define amdgpu_ps void @store_load_sindex_foo(i32 inreg %idx) {
 ;
 ; GFX942-LABEL: store_load_sindex_foo:
 ; GFX942:       ; %bb.0: ; %bb
-; GFX942-NEXT:    s_mov_b32 s2, 15
 ; GFX942-NEXT:    s_lshl_b32 s1, s0, 2
-; GFX942-NEXT:    v_mov_b32_e32 v0, s2
+; GFX942-NEXT:    v_mov_b32_e32 v0, 15
 ; GFX942-NEXT:    s_and_b32 s0, s0, 15
 ; GFX942-NEXT:    scratch_store_dword off, v0, s1 sc0 sc1
 ; GFX942-NEXT:    s_waitcnt vmcnt(0)
@@ -1590,8 +1588,7 @@ define amdgpu_kernel void @store_load_sindex_small_offset_kernel(i32 %idx) {
 ; GFX942-NEXT:    s_load_dword s0, s[4:5], 0x24
 ; GFX942-NEXT:    scratch_load_dword v0, off, off sc0 sc1
 ; GFX942-NEXT:    s_waitcnt vmcnt(0)
-; GFX942-NEXT:    s_mov_b32 s1, 15
-; GFX942-NEXT:    v_mov_b32_e32 v0, s1
+; GFX942-NEXT:    v_mov_b32_e32 v0, 15
 ; GFX942-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX942-NEXT:    s_lshl_b32 s1, s0, 2
 ; GFX942-NEXT:    s_and_b32 s0, s0, 15
@@ -1808,10 +1805,9 @@ define amdgpu_ps void @store_load_sindex_small_offset_foo(i32 inreg %idx) {
 ; GFX942-NEXT:    scratch_load_dword v0, off, off sc0 sc1
 ; GFX942-NEXT:    s_waitcnt vmcnt(0)
 ; GFX942-NEXT:    s_lshl_b32 s1, s0, 2
-; GFX942-NEXT:    s_mov_b32 s2, 15
 ; GFX942-NEXT:    s_and_b32 s0, s0, 15
 ; GFX942-NEXT:    s_addk_i32 s1, 0x100
-; GFX942-NEXT:    v_mov_b32_e32 v0, s2
+; GFX942-NEXT:    v_mov_b32_e32 v0, 15
 ; GFX942-NEXT:    s_lshl_b32 s0, s0, 2
 ; GFX942-NEXT:    scratch_store_dword off, v0, s1 sc0 sc1
 ; GFX942-NEXT:    s_waitcnt vmcnt(0)
@@ -2888,8 +2884,7 @@ define amdgpu_kernel void @store_load_sindex_large_offset_kernel(i32 %idx) {
 ; GFX942-NEXT:    s_load_dword s0, s[4:5], 0x24
 ; GFX942-NEXT:    scratch_load_dword v0, off, off offset:4 sc0 sc1
 ; GFX942-NEXT:    s_waitcnt vmcnt(0)
-; GFX942-NEXT:    s_mov_b32 s1, 15
-; GFX942-NEXT:    v_mov_b32_e32 v0, s1
+; GFX942-NEXT:    v_mov_b32_e32 v0, 15
 ; GFX942-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX942-NEXT:    s_lshl_b32 s1, s0, 2
 ; GFX942-NEXT:    s_and_b32 s0, s0, 15
@@ -3106,10 +3101,9 @@ define amdgpu_ps void @store_load_sindex_large_offset_foo(i32 inreg %idx) {
 ; GFX942-NEXT:    scratch_load_dword v0, off, off offset:4 sc0 sc1
 ; GFX942-NEXT:    s_waitcnt vmcnt(0)
 ; GFX942-NEXT:    s_lshl_b32 s1, s0, 2
-; GFX942-NEXT:    s_mov_b32 s2, 15
 ; GFX942-NEXT:    s_and_b32 s0, s0, 15
 ; GFX942-NEXT:    s_addk_i32 s1, 0x4004
-; GFX942-NEXT:    v_mov_b32_e32 v0, s2
+; GFX942-NEXT:    v_mov_b32_e32 v0, 15
 ; GFX942-NEXT:    s_lshl_b32 s0, s0, 2
 ; GFX942-NEXT:    scratch_store_dword off, v0, s1 sc0 sc1
 ; GFX942-NEXT:    s_waitcnt vmcnt(0)