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[TTI][ASan][RISCV] reland Move InterestingMemoryOperand to Analysis and embed in MemIntrinsicInfo llvm#157863 (llvm#159713)
[Previously reverted due to failures on asan-rvv-intrinsics.ll, the test case is riscv only and it is triggered by other target] Reland [llvm#157863](llvm#157863), and add `; REQUIRES: riscv-registered-target` in test case to skip the configuration that doesn't register riscv target. Previously asan considers target intrinsics as black boxes, so asan could not instrument accurate check. This patch make SmallVector<InterestingMemoryOperand> a member of MemIntrinsicInfo so that TTI can make targets describe their intrinsic informations to asan. Note, 1. This patch move InterestingMemoryOperand from Transforms to Analysis. 2. Extend MemIntrinsicInfo by adding a SmallVector<InterestingMemoryOperand> member. 3. This patch does not support RVV indexed/segment load/store.
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‎llvm/include/llvm/Analysis/InterestingMemoryOperand.h‎

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@@ -0,0 +1,55 @@
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//===- InterestingMemoryOperand.h -------------------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines InterestingMemoryOperand class that is used when getting
10+
// the information of a memory reference instruction.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_ANALYSIS_INTERESTINGMEMORYOPERAND_H
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#define LLVM_ANALYSIS_INTERESTINGMEMORYOPERAND_H
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#include "llvm/IR/DataLayout.h"
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#include "llvm/IR/Instruction.h"
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#include "llvm/Support/TypeSize.h"
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namespace llvm {
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class InterestingMemoryOperand {
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public:
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Use *PtrUse;
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bool IsWrite;
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Type *OpType;
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TypeSize TypeStoreSize = TypeSize::getFixed(0);
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MaybeAlign Alignment;
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// The mask Value, if we're looking at a masked load/store.
30+
Value *MaybeMask;
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// The EVL Value, if we're looking at a vp intrinsic.
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Value *MaybeEVL;
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// The Stride Value, if we're looking at a strided load/store.
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Value *MaybeStride;
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36+
InterestingMemoryOperand(Instruction *I, unsigned OperandNo, bool IsWrite,
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class Type *OpType, MaybeAlign Alignment,
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Value *MaybeMask = nullptr,
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Value *MaybeEVL = nullptr,
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Value *MaybeStride = nullptr)
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: IsWrite(IsWrite), OpType(OpType), Alignment(Alignment),
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MaybeMask(MaybeMask), MaybeEVL(MaybeEVL), MaybeStride(MaybeStride) {
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const DataLayout &DL = I->getDataLayout();
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TypeStoreSize = DL.getTypeStoreSizeInBits(OpType);
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PtrUse = &I->getOperandUse(OperandNo);
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}
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Instruction *getInsn() { return cast<Instruction>(PtrUse->getUser()); }
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Value *getPtr() { return PtrUse->get(); }
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};
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} // namespace llvm
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#endif // LLVM_ANALYSIS_INTERESTINGMEMORYOPERAND_H

‎llvm/include/llvm/Analysis/TargetTransformInfo.h‎

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@@ -25,6 +25,7 @@
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/BitmaskEnum.h"
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#include "llvm/Analysis/IVDescriptors.h"
28+
#include "llvm/Analysis/InterestingMemoryOperand.h"
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#include "llvm/IR/FMF.h"
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#include "llvm/IR/InstrTypes.h"
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#include "llvm/IR/PassManager.h"
@@ -88,6 +89,8 @@ struct MemIntrinsicInfo {
8889
bool WriteMem = false;
8990
bool IsVolatile = false;
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92+
SmallVector<InterestingMemoryOperand, 1> InterestingOperands;
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9194
bool isUnordered() const {
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return (Ordering == AtomicOrdering::NotAtomic ||
9396
Ordering == AtomicOrdering::Unordered) &&

‎llvm/include/llvm/Transforms/Instrumentation/AddressSanitizerCommon.h‎

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@@ -14,45 +14,14 @@
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#define LLVM_TRANSFORMS_INSTRUMENTATION_ADDRESSSANITIZERCOMMON_H
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#include "llvm/Analysis/CFG.h"
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#include "llvm/Analysis/InterestingMemoryOperand.h"
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#include "llvm/Analysis/PostDominators.h"
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#include "llvm/IR/Dominators.h"
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#include "llvm/IR/Instruction.h"
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#include "llvm/IR/IntrinsicInst.h"
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#include "llvm/IR/Module.h"
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2324
namespace llvm {
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class InterestingMemoryOperand {
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public:
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Use *PtrUse;
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bool IsWrite;
29-
Type *OpType;
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TypeSize TypeStoreSize = TypeSize::getFixed(0);
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MaybeAlign Alignment;
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// The mask Value, if we're looking at a masked load/store.
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Value *MaybeMask;
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// The EVL Value, if we're looking at a vp intrinsic.
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Value *MaybeEVL;
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// The Stride Value, if we're looking at a strided load/store.
37-
Value *MaybeStride;
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39-
InterestingMemoryOperand(Instruction *I, unsigned OperandNo, bool IsWrite,
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class Type *OpType, MaybeAlign Alignment,
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Value *MaybeMask = nullptr,
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Value *MaybeEVL = nullptr,
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Value *MaybeStride = nullptr)
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: IsWrite(IsWrite), OpType(OpType), Alignment(Alignment),
45-
MaybeMask(MaybeMask), MaybeEVL(MaybeEVL), MaybeStride(MaybeStride) {
46-
const DataLayout &DL = I->getDataLayout();
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TypeStoreSize = DL.getTypeStoreSizeInBits(OpType);
48-
PtrUse = &I->getOperandUse(OperandNo);
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}
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51-
Instruction *getInsn() { return cast<Instruction>(PtrUse->getUser()); }
52-
53-
Value *getPtr() { return PtrUse->get(); }
54-
};
55-
5625
// Get AddressSanitizer parameters.
5726
void getAddressSanitizerParams(const Triple &TargetTriple, int LongSize,
5827
bool IsKasan, uint64_t *ShadowBase,

‎llvm/lib/Analysis/TargetTransformInfo.cpp‎

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@@ -7,6 +7,7 @@
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//===----------------------------------------------------------------------===//
88

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#include "llvm/Analysis/TargetTransformInfo.h"
10+
#include "llvm/ADT/SmallVector.h"
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#include "llvm/Analysis/CFG.h"
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#include "llvm/Analysis/LoopIterator.h"
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#include "llvm/Analysis/TargetLibraryInfo.h"

‎llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp‎

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@@ -15,6 +15,7 @@
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#include "llvm/CodeGen/TargetLowering.h"
1616
#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/IR/Instructions.h"
18+
#include "llvm/IR/IntrinsicsRISCV.h"
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#include "llvm/IR/PatternMatch.h"
1920
#include <cmath>
2021
#include <optional>
@@ -2701,6 +2702,82 @@ void RISCVTTIImpl::getPeelingPreferences(Loop *L, ScalarEvolution &SE,
27012702
BaseT::getPeelingPreferences(L, SE, PP);
27022703
}
27032704

2705+
bool RISCVTTIImpl::getTgtMemIntrinsic(IntrinsicInst *Inst,
2706+
MemIntrinsicInfo &Info) const {
2707+
const DataLayout &DL = getDataLayout();
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Intrinsic::ID IID = Inst->getIntrinsicID();
2709+
LLVMContext &C = Inst->getContext();
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bool HasMask = false;
2711+
switch (IID) {
2712+
case Intrinsic::riscv_vle_mask:
2713+
case Intrinsic::riscv_vse_mask:
2714+
HasMask = true;
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[[fallthrough]];
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case Intrinsic::riscv_vle:
2717+
case Intrinsic::riscv_vse: {
2718+
// Intrinsic interface:
2719+
// riscv_vle(merge, ptr, vl)
2720+
// riscv_vle_mask(merge, ptr, mask, vl, policy)
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// riscv_vse(val, ptr, vl)
2722+
// riscv_vse_mask(val, ptr, mask, vl, policy)
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bool IsWrite = Inst->getType()->isVoidTy();
2724+
Type *Ty = IsWrite ? Inst->getArgOperand(0)->getType() : Inst->getType();
2725+
const auto *RVVIInfo = RISCVVIntrinsicsTable::getRISCVVIntrinsicInfo(IID);
2726+
unsigned VLIndex = RVVIInfo->VLOperand;
2727+
unsigned PtrOperandNo = VLIndex - 1 - HasMask;
2728+
MaybeAlign Alignment =
2729+
Inst->getArgOperand(PtrOperandNo)->getPointerAlignment(DL);
2730+
Type *MaskType = Ty->getWithNewType(Type::getInt1Ty(C));
2731+
Value *Mask = ConstantInt::getTrue(MaskType);
2732+
if (HasMask)
2733+
Mask = Inst->getArgOperand(VLIndex - 1);
2734+
Value *EVL = Inst->getArgOperand(VLIndex);
2735+
Info.InterestingOperands.emplace_back(Inst, PtrOperandNo, IsWrite, Ty,
2736+
Alignment, Mask, EVL);
2737+
return true;
2738+
}
2739+
case Intrinsic::riscv_vlse_mask:
2740+
case Intrinsic::riscv_vsse_mask:
2741+
HasMask = true;
2742+
[[fallthrough]];
2743+
case Intrinsic::riscv_vlse:
2744+
case Intrinsic::riscv_vsse: {
2745+
// Intrinsic interface:
2746+
// riscv_vlse(merge, ptr, stride, vl)
2747+
// riscv_vlse_mask(merge, ptr, stride, mask, vl, policy)
2748+
// riscv_vsse(val, ptr, stride, vl)
2749+
// riscv_vsse_mask(val, ptr, stride, mask, vl, policy)
2750+
bool IsWrite = Inst->getType()->isVoidTy();
2751+
Type *Ty = IsWrite ? Inst->getArgOperand(0)->getType() : Inst->getType();
2752+
const auto *RVVIInfo = RISCVVIntrinsicsTable::getRISCVVIntrinsicInfo(IID);
2753+
unsigned VLIndex = RVVIInfo->VLOperand;
2754+
unsigned PtrOperandNo = VLIndex - 2 - HasMask;
2755+
MaybeAlign Alignment =
2756+
Inst->getArgOperand(PtrOperandNo)->getPointerAlignment(DL);
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2758+
Value *Stride = Inst->getArgOperand(PtrOperandNo + 1);
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// Use the pointer alignment as the element alignment if the stride is a
2760+
// multiple of the pointer alignment. Otherwise, the element alignment
2761+
// should be the greatest common divisor of pointer alignment and stride.
2762+
// For simplicity, just consider unalignment for elements.
2763+
unsigned PointerAlign = Alignment.valueOrOne().value();
2764+
if (!isa<ConstantInt>(Stride) ||
2765+
cast<ConstantInt>(Stride)->getZExtValue() % PointerAlign != 0)
2766+
Alignment = Align(1);
2767+
2768+
Type *MaskType = Ty->getWithNewType(Type::getInt1Ty(C));
2769+
Value *Mask = ConstantInt::getTrue(MaskType);
2770+
if (HasMask)
2771+
Mask = Inst->getArgOperand(VLIndex - 1);
2772+
Value *EVL = Inst->getArgOperand(VLIndex);
2773+
Info.InterestingOperands.emplace_back(Inst, PtrOperandNo, IsWrite, Ty,
2774+
Alignment, Mask, EVL, Stride);
2775+
return true;
2776+
}
2777+
}
2778+
return false;
2779+
}
2780+
27042781
unsigned RISCVTTIImpl::getRegUsageForType(Type *Ty) const {
27052782
if (Ty->isVectorTy()) {
27062783
// f16 with only zvfhmin and bf16 will be promoted to f32

‎llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h‎

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@@ -160,6 +160,9 @@ class RISCVTTIImpl final : public BasicTTIImplBase<RISCVTTIImpl> {
160160
void getPeelingPreferences(Loop *L, ScalarEvolution &SE,
161161
TTI::PeelingPreferences &PP) const override;
162162

163+
bool getTgtMemIntrinsic(IntrinsicInst *Inst,
164+
MemIntrinsicInfo &Info) const override;
165+
163166
unsigned getMinVectorRegisterBitWidth() const override {
164167
return ST->useRVVForFixedLengthVectors() ? 16 : 0;
165168
}

‎llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp‎

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Original file line numberDiff line numberDiff line change
@@ -29,6 +29,7 @@
2929
#include "llvm/Analysis/MemoryBuiltins.h"
3030
#include "llvm/Analysis/StackSafetyAnalysis.h"
3131
#include "llvm/Analysis/TargetLibraryInfo.h"
32+
#include "llvm/Analysis/TargetTransformInfo.h"
3233
#include "llvm/Analysis/ValueTracking.h"
3334
#include "llvm/BinaryFormat/MachO.h"
3435
#include "llvm/Demangle/Demangle.h"
@@ -803,7 +804,8 @@ struct AddressSanitizer {
803804

804805
bool ignoreAccess(Instruction *Inst, Value *Ptr);
805806
void getInterestingMemoryOperands(
806-
Instruction *I, SmallVectorImpl<InterestingMemoryOperand> &Interesting);
807+
Instruction *I, SmallVectorImpl<InterestingMemoryOperand> &Interesting,
808+
const TargetTransformInfo *TTI);
807809

808810
void instrumentMop(ObjectSizeOffsetVisitor &ObjSizeVis,
809811
InterestingMemoryOperand &O, bool UseCalls,
@@ -843,7 +845,8 @@ struct AddressSanitizer {
843845
void instrumentMemIntrinsic(MemIntrinsic *MI, RuntimeCallInserter &RTCI);
844846
Value *memToShadow(Value *Shadow, IRBuilder<> &IRB);
845847
bool suppressInstrumentationSiteForDebug(int &Instrumented);
846-
bool instrumentFunction(Function &F, const TargetLibraryInfo *TLI);
848+
bool instrumentFunction(Function &F, const TargetLibraryInfo *TLI,
849+
const TargetTransformInfo *TTI);
847850
bool maybeInsertAsanInitAtFunctionEntry(Function &F);
848851
bool maybeInsertDynamicShadowAtFunctionEntry(Function &F);
849852
void markEscapedLocalAllocas(Function &F);
@@ -1314,7 +1317,8 @@ PreservedAnalyses AddressSanitizerPass::run(Module &M,
13141317
Options.MaxInlinePoisoningSize, Options.CompileKernel, Options.Recover,
13151318
Options.UseAfterScope, Options.UseAfterReturn);
13161319
const TargetLibraryInfo &TLI = FAM.getResult<TargetLibraryAnalysis>(F);
1317-
Modified |= FunctionSanitizer.instrumentFunction(F, &TLI);
1320+
const TargetTransformInfo &TTI = FAM.getResult<TargetIRAnalysis>(F);
1321+
Modified |= FunctionSanitizer.instrumentFunction(F, &TLI, &TTI);
13181322
}
13191323
Modified |= ModuleSanitizer.instrumentModule();
13201324
if (!Modified)
@@ -1452,7 +1456,8 @@ bool AddressSanitizer::ignoreAccess(Instruction *Inst, Value *Ptr) {
14521456
}
14531457

14541458
void AddressSanitizer::getInterestingMemoryOperands(
1455-
Instruction *I, SmallVectorImpl<InterestingMemoryOperand> &Interesting) {
1459+
Instruction *I, SmallVectorImpl<InterestingMemoryOperand> &Interesting,
1460+
const TargetTransformInfo *TTI) {
14561461
// Do not instrument the load fetching the dynamic shadow address.
14571462
if (LocalDynamicShadow == I)
14581463
return;
@@ -1570,6 +1575,12 @@ void AddressSanitizer::getInterestingMemoryOperands(
15701575
break;
15711576
}
15721577
default:
1578+
if (auto *II = dyn_cast<IntrinsicInst>(I)) {
1579+
MemIntrinsicInfo IntrInfo;
1580+
if (TTI->getTgtMemIntrinsic(II, IntrInfo))
1581+
Interesting = IntrInfo.InterestingOperands;
1582+
return;
1583+
}
15731584
for (unsigned ArgNo = 0; ArgNo < CI->arg_size(); ArgNo++) {
15741585
if (!ClInstrumentByval || !CI->isByValArgument(ArgNo) ||
15751586
ignoreAccess(I, CI->getArgOperand(ArgNo)))
@@ -2985,7 +2996,8 @@ bool AddressSanitizer::suppressInstrumentationSiteForDebug(int &Instrumented) {
29852996
}
29862997

29872998
bool AddressSanitizer::instrumentFunction(Function &F,
2988-
const TargetLibraryInfo *TLI) {
2999+
const TargetLibraryInfo *TLI,
3000+
const TargetTransformInfo *TTI) {
29893001
bool FunctionModified = false;
29903002

29913003
// Do not apply any instrumentation for naked functions.
@@ -3038,7 +3050,7 @@ bool AddressSanitizer::instrumentFunction(Function &F,
30383050
if (Inst.hasMetadata(LLVMContext::MD_nosanitize))
30393051
continue;
30403052
SmallVector<InterestingMemoryOperand, 1> InterestingOperands;
3041-
getInterestingMemoryOperands(&Inst, InterestingOperands);
3053+
getInterestingMemoryOperands(&Inst, InterestingOperands, TTI);
30423054

30433055
if (!InterestingOperands.empty()) {
30443056
for (auto &Operand : InterestingOperands) {

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