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[CodeGen][AArch64] Ensure isSExtCheaperThanZExt returns true for negative constants
When we know the value we're extending is a negative constant then it makes sense to use SIGN_EXTEND because this may improve code quality in some cases, particularly when doing a constant splat of an unpacked vector type. For example, for SVE when splatting the value -1 into all elements of a vector of type <vscale x 2 x i32> the element type will get promoted from i32 -> i64. In this case we want the splat value to sign-extend from (i32 -1) -> (i64 -1), whereas currently it zero-extends from (i32 -1) -> (i64 0xFFFFFFFF). Sign-extending the constant means we can use a single mov immediate instruction. New tests added here: CodeGen/AArch64/sve-vector-splat.ll I believe we see some code quality improvements in these existing tests too: CodeGen/AArch64/reduce-and.ll CodeGen/AArch64/unfold-masked-merge-vector-variablemask.ll The apparent regressions in CodeGen/AArch64/fast-isel-cmp-vec.ll only occur because the test disables codegen prepare and branch folding. Differential Revision: https://reviews.llvm.org/D114357
1 parent 5f2edad commit 197f3c0

14 files changed

+35
-47
lines changed

‎llvm/include/llvm/CodeGen/TargetLowering.h

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2647,9 +2647,9 @@ class TargetLoweringBase {
26472647
getApproximateEVTForLLT(ToTy, DL, Ctx));
26482648
}
26492649

2650-
/// Return true if sign-extension from FromTy to ToTy is cheaper than
2651-
/// zero-extension.
2652-
virtual bool isSExtCheaperThanZExt(EVT FromTy, EVT ToTy) const {
2650+
/// Return true if sign-extension of value \p V from FromTy to ToTy is
2651+
/// cheaper than zero-extension, where \p V can be SDValue() if unknown.
2652+
virtual bool isSExtCheaperThanZExt(EVT FromTy, EVT ToTy, SDValue V) const {
26532653
return false;
26542654
}
26552655

‎llvm/lib/CodeGen/CodeGenPrepare.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7004,7 +7004,7 @@ bool CodeGenPrepare::optimizeSwitchInst(SwitchInst *SI) {
70047004
// matching the argument extension instead.
70057005
Instruction::CastOps ExtType = Instruction::ZExt;
70067006
// Some targets prefer SExt over ZExt.
7007-
if (TLI->isSExtCheaperThanZExt(OldVT, RegType))
7007+
if (TLI->isSExtCheaperThanZExt(OldVT, RegType, SDValue()))
70087008
ExtType = Instruction::SExt;
70097009

70107010
if (auto *Arg = dyn_cast<Argument>(Cond)) {

‎llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1704,7 +1704,7 @@ void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &LHS, SDValue &RHS,
17041704
SDValue OpL = GetPromotedInteger(LHS);
17051705
SDValue OpR = GetPromotedInteger(RHS);
17061706

1707-
if (TLI.isSExtCheaperThanZExt(LHS.getValueType(), OpL.getValueType())) {
1707+
if (TLI.isSExtCheaperThanZExt(LHS.getValueType(), OpL.getValueType(), LHS)) {
17081708
// The target would prefer to promote the comparison operand with sign
17091709
// extension. Honor that unless the promoted values are already zero
17101710
// extended.

‎llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -283,7 +283,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
283283
EVT OldVT = Op.getValueType();
284284
SDLoc DL(Op);
285285
Op = GetPromotedInteger(Op);
286-
if (TLI.isSExtCheaperThanZExt(OldVT, Op.getValueType()))
286+
if (TLI.isSExtCheaperThanZExt(OldVT, Op.getValueType(), Op))
287287
return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Op.getValueType(), Op,
288288
DAG.getValueType(OldVT));
289289
return DAG.getZeroExtendInReg(Op, DL, OldVT);

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4765,7 +4765,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
47654765
C->isTargetOpcode(), C->isOpaque());
47664766
case ISD::ANY_EXTEND:
47674767
// Some targets like RISCV prefer to sign extend some types.
4768-
if (TLI->isSExtCheaperThanZExt(Operand.getValueType(), VT))
4768+
if (TLI->isSExtCheaperThanZExt(Operand.getValueType(), VT, Operand))
47694769
return getConstant(Val.sextOrTrunc(VT.getSizeInBits()), DL, VT,
47704770
C->isTargetOpcode(), C->isOpaque());
47714771
return getConstant(Val.zextOrTrunc(VT.getSizeInBits()), DL, VT,

‎llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3844,7 +3844,7 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
38443844
} else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
38453845
(Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
38463846
!isSExtCheaperThanZExt(cast<VTSDNode>(N0.getOperand(1))->getVT(),
3847-
OpVT)) {
3847+
OpVT, N0.getOperand(1))) {
38483848
EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
38493849
unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
38503850
EVT ExtDstTy = N0.getValueType();

‎llvm/lib/Target/AArch64/AArch64ISelLowering.h

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1138,6 +1138,14 @@ class AArch64TargetLowering : public TargetLowering {
11381138

11391139
bool isConstantUnsignedBitfieldExtractLegal(unsigned Opc, LLT Ty1,
11401140
LLT Ty2) const override;
1141+
1142+
bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT, SDValue V) const override {
1143+
if (!V || SrcVT.getScalarType() == MVT::i1)
1144+
return false;
1145+
if (ConstantSDNode *C = isConstOrConstSplat(V))
1146+
return C->getAPIntValue().isNegative();
1147+
return false;
1148+
}
11411149
};
11421150

11431151
namespace AArch64 {

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1198,7 +1198,8 @@ bool RISCVTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
11981198
return TargetLowering::isZExtFree(Val, VT2);
11991199
}
12001200

1201-
bool RISCVTargetLowering::isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const {
1201+
bool RISCVTargetLowering::isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT,
1202+
SDValue V) const {
12021203
return Subtarget.is64Bit() && SrcVT == MVT::i32 && DstVT == MVT::i64;
12031204
}
12041205

‎llvm/lib/Target/RISCV/RISCVISelLowering.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -326,7 +326,7 @@ class RISCVTargetLowering : public TargetLowering {
326326
bool isTruncateFree(Type *SrcTy, Type *DstTy) const override;
327327
bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
328328
bool isZExtFree(SDValue Val, EVT VT2) const override;
329-
bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override;
329+
bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT, SDValue V) const override;
330330
bool isCheapToSpeculateCttz() const override;
331331
bool isCheapToSpeculateCtlz() const override;
332332
bool hasAndNotCompare(SDValue Y) const override;

‎llvm/test/CodeGen/AArch64/funnel-shift.ll

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -93,7 +93,7 @@ declare i7 @llvm.fshl.i7(i7, i7, i7)
9393
define i7 @fshl_i7_const_fold() {
9494
; CHECK-LABEL: fshl_i7_const_fold:
9595
; CHECK: // %bb.0:
96-
; CHECK-NEXT: mov w0, #67
96+
; CHECK-NEXT: mov w0, #-61
9797
; CHECK-NEXT: ret
9898
%f = call i7 @llvm.fshl.i7(i7 112, i7 127, i7 2)
9999
ret i7 %f
@@ -102,7 +102,7 @@ define i7 @fshl_i7_const_fold() {
102102
define i8 @fshl_i8_const_fold_overshift_1() {
103103
; CHECK-LABEL: fshl_i8_const_fold_overshift_1:
104104
; CHECK: // %bb.0:
105-
; CHECK-NEXT: mov w0, #128
105+
; CHECK-NEXT: mov w0, #-128
106106
; CHECK-NEXT: ret
107107
%f = call i8 @llvm.fshl.i8(i8 255, i8 0, i8 15)
108108
ret i8 %f
@@ -164,7 +164,7 @@ define i64 @fshl_i64_const_overshift(i64 %x, i64 %y) {
164164
define i8 @fshl_i8_const_fold() {
165165
; CHECK-LABEL: fshl_i8_const_fold:
166166
; CHECK: // %bb.0:
167-
; CHECK-NEXT: mov w0, #128
167+
; CHECK-NEXT: mov w0, #-128
168168
; CHECK-NEXT: ret
169169
%f = call i8 @llvm.fshl.i8(i8 255, i8 0, i8 7)
170170
ret i8 %f
@@ -241,7 +241,7 @@ define i7 @fshr_i7_const_fold() {
241241
define i8 @fshr_i8_const_fold_overshift_1() {
242242
; CHECK-LABEL: fshr_i8_const_fold_overshift_1:
243243
; CHECK: // %bb.0:
244-
; CHECK-NEXT: mov w0, #254
244+
; CHECK-NEXT: mov w0, #-2
245245
; CHECK-NEXT: ret
246246
%f = call i8 @llvm.fshr.i8(i8 255, i8 0, i8 15)
247247
ret i8 %f
@@ -250,7 +250,7 @@ define i8 @fshr_i8_const_fold_overshift_1() {
250250
define i8 @fshr_i8_const_fold_overshift_2() {
251251
; CHECK-LABEL: fshr_i8_const_fold_overshift_2:
252252
; CHECK: // %bb.0:
253-
; CHECK-NEXT: mov w0, #225
253+
; CHECK-NEXT: mov w0, #-31
254254
; CHECK-NEXT: ret
255255
%f = call i8 @llvm.fshr.i8(i8 15, i8 15, i8 11)
256256
ret i8 %f
@@ -259,7 +259,7 @@ define i8 @fshr_i8_const_fold_overshift_2() {
259259
define i8 @fshr_i8_const_fold_overshift_3() {
260260
; CHECK-LABEL: fshr_i8_const_fold_overshift_3:
261261
; CHECK: // %bb.0:
262-
; CHECK-NEXT: mov w0, #255
262+
; CHECK-NEXT: mov w0, #-1
263263
; CHECK-NEXT: ret
264264
%f = call i8 @llvm.fshr.i8(i8 0, i8 255, i8 8)
265265
ret i8 %f
@@ -303,7 +303,7 @@ define i64 @fshr_i64_const_overshift(i64 %x, i64 %y) {
303303
define i8 @fshr_i8_const_fold() {
304304
; CHECK-LABEL: fshr_i8_const_fold:
305305
; CHECK: // %bb.0:
306-
; CHECK-NEXT: mov w0, #254
306+
; CHECK-NEXT: mov w0, #-2
307307
; CHECK-NEXT: ret
308308
%f = call i8 @llvm.fshr.i8(i8 255, i8 0, i8 7)
309309
ret i8 %f

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