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[NFC][SVE] Add missing tests for i32 INC/DEC patterns.
D111441 included trunc isel patterns for sve_int_pred_pattern_a but no accompanying tests. This patch adds the missing tests and also simplifies the isel patterns that use sve_cnt_shl_imm. Differential Revision: https://reviews.llvm.org/D115512
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-4
lines changed

2 files changed

+355
-4
lines changed

‎llvm/lib/Target/AArch64/SVEInstrFormats.td

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -272,7 +272,6 @@ def sve_cnt_mul_imm_i32 : ComplexPattern<i32, 1, "SelectCntImm<1, 16, 1, false>"
272272
def sve_cnt_mul_imm_i64 : ComplexPattern<i64, 1, "SelectCntImm<1, 16, 1, false>">;
273273
def sve_cnt_shl_imm : ComplexPattern<i64, 1, "SelectCntImm<1, 16, 1, true>">;
274274

275-
276275
def sve_ext_imm_0_31 : ComplexPattern<i64, 1, "SelectEXTImm<31, 8>">;
277276
def sve_ext_imm_0_63 : ComplexPattern<i64, 1, "SelectEXTImm<63, 4>">;
278277
def sve_ext_imm_0_127 : ComplexPattern<i64, 1, "SelectEXTImm<127, 2>">;
@@ -880,7 +879,7 @@ multiclass sve_int_count<bits<3> opc, string asm, SDPatternOperator op> {
880879
def : Pat<(i64 (mul (op sve_pred_enum:$pattern), (sve_cnt_mul_imm_i64 i32:$imm))),
881880
(!cast<Instruction>(NAME) sve_pred_enum:$pattern, sve_incdec_imm:$imm)>;
882881

883-
def : Pat<(i64 (shl (op sve_pred_enum:$pattern), (i64 (sve_cnt_shl_imm i32:$imm)))),
882+
def : Pat<(i64 (shl (op sve_pred_enum:$pattern), (sve_cnt_shl_imm i32:$imm))),
884883
(!cast<Instruction>(NAME) sve_pred_enum:$pattern, sve_incdec_imm:$imm)>;
885884

886885
def : Pat<(i64 (op sve_pred_enum:$pattern)),
@@ -963,7 +962,7 @@ multiclass sve_int_pred_pattern_a<bits<3> opc, string asm,
963962
def : Pat<(i64 (op GPR64:$Rdn, (mul (opcnt sve_pred_enum:$pattern), (sve_cnt_mul_imm_i64 i32:$imm)))),
964963
(!cast<Instruction>(NAME) GPR64:$Rdn, sve_pred_enum:$pattern, $imm)>;
965964

966-
def : Pat<(i64 (op GPR64:$Rdn, (shl (opcnt sve_pred_enum:$pattern), (i64 (sve_cnt_shl_imm i32:$imm))))),
965+
def : Pat<(i64 (op GPR64:$Rdn, (shl (opcnt sve_pred_enum:$pattern), (sve_cnt_shl_imm i32:$imm)))),
967966
(!cast<Instruction>(NAME) GPR64:$Rdn, sve_pred_enum:$pattern, $imm)>;
968967

969968
def : Pat<(i32 (op GPR32:$Rdn, (i32 (trunc (opcnt (sve_pred_enum:$pattern)))))),
@@ -976,7 +975,7 @@ multiclass sve_int_pred_pattern_a<bits<3> opc, string asm,
976975
GPR32:$Rdn, sub_32), sve_pred_enum:$pattern, $imm),
977976
sub_32))>;
978977

979-
def : Pat<(i32 (op GPR32:$Rdn, (shl (i32 (trunc (opcnt (sve_pred_enum:$pattern)))), (i64 (sve_cnt_shl_imm i32:$imm))))),
978+
def : Pat<(i32 (op GPR32:$Rdn, (shl (i32 (trunc (opcnt (sve_pred_enum:$pattern)))), (sve_cnt_shl_imm i32:$imm)))),
980979
(i32 (EXTRACT_SUBREG (!cast<Instruction>(NAME) (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
981980
GPR32:$Rdn, sub_32), sve_pred_enum:$pattern, $imm),
982981
sub_32))>;

‎llvm/test/CodeGen/AArch64/sve-intrinsics-counting-elems-i32.ll

Lines changed: 352 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,352 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2+
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s -check-prefix=NO_SCALAR_INC
3+
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -mattr=+use-scalar-inc-vl < %s | FileCheck %s
4+
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s
5+
6+
; INCB
7+
8+
define i32 @incb(i32 %a) {
9+
; NO_SCALAR_INC-LABEL: incb:
10+
; NO_SCALAR_INC: // %bb.0:
11+
; NO_SCALAR_INC-NEXT: cntb x8, vl5
12+
; NO_SCALAR_INC-NEXT: add w0, w8, w0
13+
; NO_SCALAR_INC-NEXT: ret
14+
;
15+
; CHECK-LABEL: incb:
16+
; CHECK: // %bb.0:
17+
; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
18+
; CHECK-NEXT: incb x0, vl5
19+
; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0
20+
; CHECK-NEXT: ret
21+
%cnt = call i64 @llvm.aarch64.sve.cntb(i32 5)
22+
%conv = trunc i64 %cnt to i32
23+
%out = add i32 %conv, %a
24+
ret i32 %out
25+
}
26+
27+
define i32 @incb_mul(i32 %a) {
28+
; NO_SCALAR_INC-LABEL: incb_mul:
29+
; NO_SCALAR_INC: // %bb.0:
30+
; NO_SCALAR_INC-NEXT: cntb x8, vl8
31+
; NO_SCALAR_INC-NEXT: add w0, w0, w8, lsl #2
32+
; NO_SCALAR_INC-NEXT: ret
33+
;
34+
; CHECK-LABEL: incb_mul:
35+
; CHECK: // %bb.0:
36+
; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
37+
; CHECK-NEXT: incb x0, vl8, mul #4
38+
; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0
39+
; CHECK-NEXT: ret
40+
%cnt = call i64 @llvm.aarch64.sve.cntb(i32 8)
41+
%conv = trunc i64 %cnt to i32
42+
%mul = mul i32 %conv, 4
43+
%out = add i32 %mul, %a
44+
ret i32 %out
45+
}
46+
47+
;
48+
; DECB
49+
;
50+
51+
define i32 @decb(i32 %a) {
52+
; NO_SCALAR_INC-LABEL: decb:
53+
; NO_SCALAR_INC: // %bb.0:
54+
; NO_SCALAR_INC-NEXT: cntb x8, vl6
55+
; NO_SCALAR_INC-NEXT: sub w0, w0, w8
56+
; NO_SCALAR_INC-NEXT: ret
57+
;
58+
; CHECK-LABEL: decb:
59+
; CHECK: // %bb.0:
60+
; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
61+
; CHECK-NEXT: decb x0, vl6
62+
; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0
63+
; CHECK-NEXT: ret
64+
%cnt = call i64 @llvm.aarch64.sve.cntb(i32 6)
65+
%conv = trunc i64 %cnt to i32
66+
%out = sub i32 %a, %conv
67+
ret i32 %out
68+
}
69+
70+
define i32 @decb_mul(i32 %a) {
71+
; NO_SCALAR_INC-LABEL: decb_mul:
72+
; NO_SCALAR_INC: // %bb.0:
73+
; NO_SCALAR_INC-NEXT: cntb x8, vl6
74+
; NO_SCALAR_INC-NEXT: sub w0, w0, w8, lsl #3
75+
; NO_SCALAR_INC-NEXT: ret
76+
;
77+
; CHECK-LABEL: decb_mul:
78+
; CHECK: // %bb.0:
79+
; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
80+
; CHECK-NEXT: decb x0, vl6, mul #8
81+
; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0
82+
; CHECK-NEXT: ret
83+
%cnt = call i64 @llvm.aarch64.sve.cntb(i32 6)
84+
%conv = trunc i64 %cnt to i32
85+
%mul = mul i32 %conv, 8
86+
%out = sub i32 %a, %mul
87+
ret i32 %out
88+
}
89+
90+
; INCH
91+
92+
define i32 @inch(i32 %a) {
93+
; NO_SCALAR_INC-LABEL: inch:
94+
; NO_SCALAR_INC: // %bb.0:
95+
; NO_SCALAR_INC-NEXT: cnth x8, #16
96+
; NO_SCALAR_INC-NEXT: add w0, w8, w0
97+
; NO_SCALAR_INC-NEXT: ret
98+
;
99+
; CHECK-LABEL: inch:
100+
; CHECK: // %bb.0:
101+
; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
102+
; CHECK-NEXT: inch x0, #16
103+
; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0
104+
; CHECK-NEXT: ret
105+
%cnt = call i64 @llvm.aarch64.sve.cnth(i32 16)
106+
%conv = trunc i64 %cnt to i32
107+
%out = add i32 %conv, %a
108+
ret i32 %out
109+
}
110+
111+
define i32 @inch_mul(i32 %a) {
112+
; NO_SCALAR_INC-LABEL: inch_mul:
113+
; NO_SCALAR_INC: // %bb.0:
114+
; NO_SCALAR_INC-NEXT: mov w8, #5
115+
; NO_SCALAR_INC-NEXT: cnth x9, vl8
116+
; NO_SCALAR_INC-NEXT: madd w0, w9, w8, w0
117+
; NO_SCALAR_INC-NEXT: ret
118+
;
119+
; CHECK-LABEL: inch_mul:
120+
; CHECK: // %bb.0:
121+
; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
122+
; CHECK-NEXT: inch x0, vl8, mul #5
123+
; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0
124+
; CHECK-NEXT: ret
125+
%cnt = call i64 @llvm.aarch64.sve.cnth(i32 8)
126+
%conv = trunc i64 %cnt to i32
127+
%mul = mul i32 %conv, 5
128+
%out = add i32 %mul, %a
129+
ret i32 %out
130+
}
131+
132+
;
133+
; DECH
134+
;
135+
136+
define i32 @dech(i32 %a) {
137+
; NO_SCALAR_INC-LABEL: dech:
138+
; NO_SCALAR_INC: // %bb.0:
139+
; NO_SCALAR_INC-NEXT: cnth x8, vl1
140+
; NO_SCALAR_INC-NEXT: sub w0, w0, w8
141+
; NO_SCALAR_INC-NEXT: ret
142+
;
143+
; CHECK-LABEL: dech:
144+
; CHECK: // %bb.0:
145+
; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
146+
; CHECK-NEXT: dech x0, vl1
147+
; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0
148+
; CHECK-NEXT: ret
149+
%cnt = call i64 @llvm.aarch64.sve.cnth(i32 1)
150+
%conv = trunc i64 %cnt to i32
151+
%out = sub i32 %a, %conv
152+
ret i32 %out
153+
}
154+
155+
define i32 @dech_mul(i32 %a) {
156+
; NO_SCALAR_INC-LABEL: dech_mul:
157+
; NO_SCALAR_INC: // %bb.0:
158+
; NO_SCALAR_INC-NEXT: mov w8, #7
159+
; NO_SCALAR_INC-NEXT: cnth x9, vl16
160+
; NO_SCALAR_INC-NEXT: msub w0, w9, w8, w0
161+
; NO_SCALAR_INC-NEXT: ret
162+
;
163+
; CHECK-LABEL: dech_mul:
164+
; CHECK: // %bb.0:
165+
; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
166+
; CHECK-NEXT: dech x0, vl16, mul #7
167+
; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0
168+
; CHECK-NEXT: ret
169+
%cnt = call i64 @llvm.aarch64.sve.cnth(i32 9)
170+
%conv = trunc i64 %cnt to i32
171+
%mul = mul i32 %conv, 7
172+
%out = sub i32 %a, %mul
173+
ret i32 %out
174+
}
175+
176+
;
177+
; INCW
178+
;
179+
180+
define i32 @incw(i32 %a) {
181+
; NO_SCALAR_INC-LABEL: incw:
182+
; NO_SCALAR_INC: // %bb.0:
183+
; NO_SCALAR_INC-NEXT: cntw x8, #16
184+
; NO_SCALAR_INC-NEXT: add w0, w8, w0
185+
; NO_SCALAR_INC-NEXT: ret
186+
;
187+
; CHECK-LABEL: incw:
188+
; CHECK: // %bb.0:
189+
; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
190+
; CHECK-NEXT: incw x0, #16
191+
; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0
192+
; CHECK-NEXT: ret
193+
%cnt = call i64 @llvm.aarch64.sve.cntw(i32 16)
194+
%conv = trunc i64 %cnt to i32
195+
%out = add i32 %conv, %a
196+
ret i32 %out
197+
}
198+
199+
define i32 @incw_mul(i32 %a) {
200+
; NO_SCALAR_INC-LABEL: incw_mul:
201+
; NO_SCALAR_INC: // %bb.0:
202+
; NO_SCALAR_INC-NEXT: mov w8, #12
203+
; NO_SCALAR_INC-NEXT: cntw x9, vl32
204+
; NO_SCALAR_INC-NEXT: madd w0, w9, w8, w0
205+
; NO_SCALAR_INC-NEXT: ret
206+
;
207+
; CHECK-LABEL: incw_mul:
208+
; CHECK: // %bb.0:
209+
; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
210+
; CHECK-NEXT: incw x0, vl32, mul #12
211+
; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0
212+
; CHECK-NEXT: ret
213+
%cnt = call i64 @llvm.aarch64.sve.cntw(i32 10)
214+
%conv = trunc i64 %cnt to i32
215+
%mul = mul i32 %conv, 12
216+
%out = add i32 %mul, %a
217+
ret i32 %out
218+
}
219+
220+
;
221+
; DECW
222+
;
223+
224+
define i32 @decw(i32 %a) {
225+
; NO_SCALAR_INC-LABEL: decw:
226+
; NO_SCALAR_INC: // %bb.0:
227+
; NO_SCALAR_INC-NEXT: cntw x8, vl64
228+
; NO_SCALAR_INC-NEXT: sub w0, w0, w8
229+
; NO_SCALAR_INC-NEXT: ret
230+
;
231+
; CHECK-LABEL: decw:
232+
; CHECK: // %bb.0:
233+
; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
234+
; CHECK-NEXT: decw x0, vl64
235+
; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0
236+
; CHECK-NEXT: ret
237+
%cnt = call i64 @llvm.aarch64.sve.cntw(i32 11)
238+
%conv = trunc i64 %cnt to i32
239+
%out = sub i32 %a, %conv
240+
ret i32 %out
241+
}
242+
243+
define i32 @decw_mul(i32 %a) {
244+
; NO_SCALAR_INC-LABEL: decw_mul:
245+
; NO_SCALAR_INC: // %bb.0:
246+
; NO_SCALAR_INC-NEXT: cntw x8, vl128
247+
; NO_SCALAR_INC-NEXT: sub w0, w0, w8, lsl #4
248+
; NO_SCALAR_INC-NEXT: ret
249+
;
250+
; CHECK-LABEL: decw_mul:
251+
; CHECK: // %bb.0:
252+
; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
253+
; CHECK-NEXT: decw x0, vl128, mul #16
254+
; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0
255+
; CHECK-NEXT: ret
256+
%cnt = call i64 @llvm.aarch64.sve.cntw(i32 12)
257+
%conv = trunc i64 %cnt to i32
258+
%mul = mul i32 %conv, 16
259+
%out = sub i32 %a, %mul
260+
ret i32 %out
261+
}
262+
263+
; INCD
264+
265+
define i32 @incd(i32 %base) {
266+
; NO_SCALAR_INC-LABEL: incd:
267+
; NO_SCALAR_INC: // %bb.0:
268+
; NO_SCALAR_INC-NEXT: cntd x8, vl64
269+
; NO_SCALAR_INC-NEXT: add w0, w0, w8
270+
; NO_SCALAR_INC-NEXT: ret
271+
;
272+
; CHECK-LABEL: incd:
273+
; CHECK: // %bb.0:
274+
; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
275+
; CHECK-NEXT: incd x0, vl64
276+
; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0
277+
; CHECK-NEXT: ret
278+
%cnt = tail call i64 @llvm.aarch64.sve.cntd(i32 11)
279+
%conv = trunc i64 %cnt to i32
280+
%add = add i32 %base, %conv
281+
ret i32 %add
282+
}
283+
284+
define i32 @incd_mul(i32 %base) {
285+
; NO_SCALAR_INC-LABEL: incd_mul:
286+
; NO_SCALAR_INC: // %bb.0:
287+
; NO_SCALAR_INC-NEXT: mov w8, #15
288+
; NO_SCALAR_INC-NEXT: cntd x9, vl64
289+
; NO_SCALAR_INC-NEXT: madd w0, w9, w8, w0
290+
; NO_SCALAR_INC-NEXT: ret
291+
;
292+
; CHECK-LABEL: incd_mul:
293+
; CHECK: // %bb.0:
294+
; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
295+
; CHECK-NEXT: incd x0, vl64, mul #15
296+
; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0
297+
; CHECK-NEXT: ret
298+
%cnt = tail call i64 @llvm.aarch64.sve.cntd(i32 11)
299+
%conv = trunc i64 %cnt to i32
300+
%mul = mul i32 %conv, 15
301+
%add = add i32 %base, %mul
302+
ret i32 %add
303+
}
304+
305+
;
306+
; DECD
307+
;
308+
309+
define i32 @decd(i32 %a) {
310+
; NO_SCALAR_INC-LABEL: decd:
311+
; NO_SCALAR_INC: // %bb.0:
312+
; NO_SCALAR_INC-NEXT: cntd x8, #16
313+
; NO_SCALAR_INC-NEXT: sub w0, w0, w8
314+
; NO_SCALAR_INC-NEXT: ret
315+
;
316+
; CHECK-LABEL: decd:
317+
; CHECK: // %bb.0:
318+
; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
319+
; CHECK-NEXT: decd x0, #16
320+
; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0
321+
; CHECK-NEXT: ret
322+
%cnt = call i64 @llvm.aarch64.sve.cntd(i32 16)
323+
%conv = trunc i64 %cnt to i32
324+
%out = sub i32 %a, %conv
325+
ret i32 %out
326+
}
327+
328+
define i32 @decd_mul(i32 %a) {
329+
; NO_SCALAR_INC-LABEL: decd_mul:
330+
; NO_SCALAR_INC: // %bb.0:
331+
; NO_SCALAR_INC-NEXT: mov w8, #9
332+
; NO_SCALAR_INC-NEXT: cntd x9, vl2
333+
; NO_SCALAR_INC-NEXT: msub w0, w9, w8, w0
334+
; NO_SCALAR_INC-NEXT: ret
335+
;
336+
; CHECK-LABEL: decd_mul:
337+
; CHECK: // %bb.0:
338+
; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
339+
; CHECK-NEXT: decd x0, vl2, mul #9
340+
; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0
341+
; CHECK-NEXT: ret
342+
%cnt = call i64 @llvm.aarch64.sve.cntd(i32 2)
343+
%conv = trunc i64 %cnt to i32
344+
%mul = mul i32 %conv, 9
345+
%out = sub i32 %a, %mul
346+
ret i32 %out
347+
}
348+
349+
declare i64 @llvm.aarch64.sve.cntb(i32 %pattern)
350+
declare i64 @llvm.aarch64.sve.cnth(i32 %pattern)
351+
declare i64 @llvm.aarch64.sve.cntw(i32 %pattern)
352+
declare i64 @llvm.aarch64.sve.cntd(i32 %pattern)

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