[VE] Update a regression test

Update CodeGen/VE/Vector/fastcc_callee.ll regression test since
register allocation or something are changed.

Author: kaz7

llvm/test/CodeGen/VE/Vector/fastcc_callee.ll

@@ -307,114 +307,114 @@ define fastcc <17 x i65> @vreg_arg_v17i65_r1(<256 x i65> %p0, <17 x i65> %p1) {
 ; CHECK-NEXT:    ld %s6, 4344(, %s11)
 ; CHECK-NEXT:    ld %s35, 4368(, %s11)
 ; CHECK-NEXT:    ld %s34, 4360(, %s11)
-; CHECK-NEXT:    ld %s38, 4384(, %s11)
+; CHECK-NEXT:    ld %s37, 4384(, %s11)
 ; CHECK-NEXT:    ld %s36, 4376(, %s11)
-; CHECK-NEXT:    ld %s39, 4400(, %s11)
-; CHECK-NEXT:    ld %s40, 4392(, %s11)
-; CHECK-NEXT:    ld %s41, 4416(, %s11)
-; CHECK-NEXT:    ld %s42, 4408(, %s11)
-; CHECK-NEXT:    ld %s43, 4432(, %s11)
-; CHECK-NEXT:    ld %s44, 4424(, %s11)
-; CHECK-NEXT:    ld %s45, 4448(, %s11)
-; CHECK-NEXT:    ld %s46, 4440(, %s11)
-; CHECK-NEXT:    ld %s47, 4464(, %s11)
-; CHECK-NEXT:    ld %s48, 4456(, %s11)
-; CHECK-NEXT:    ld %s49, 4480(, %s11)
-; CHECK-NEXT:    ld %s50, 4472(, %s11)
-; CHECK-NEXT:    ld %s51, 4496(, %s11)
-; CHECK-NEXT:    ld %s52, 4488(, %s11)
-; CHECK-NEXT:    ld %s53, 4512(, %s11)
-; CHECK-NEXT:    ld %s54, 4504(, %s11)
-; CHECK-NEXT:    ld %s55, 4528(, %s11)
-; CHECK-NEXT:    ld %s56, 4520(, %s11)
-; CHECK-NEXT:    ld %s57, 4288(, %s11)
-; CHECK-NEXT:    ld %s58, 4280(, %s11)
-; CHECK-NEXT:    ld %s59, 4544(, %s11)
-; CHECK-NEXT:    ld %s37, 4296(, %s11)
-; CHECK-NEXT:    ld %s60, 4536(, %s11)
-; CHECK-NEXT:    st %s58, (, %s0)
-; CHECK-NEXT:    and %s58, 1, %s59
-; CHECK-NEXT:    st1b %s58, 138(, %s0)
-; CHECK-NEXT:    srl %s58, %s60, 48
-; CHECK-NEXT:    st2b %s58, 136(, %s0)
-; CHECK-NEXT:    sll %s58, %s37, 1
+; CHECK-NEXT:    ld %s38, 4400(, %s11)
+; CHECK-NEXT:    ld %s39, 4392(, %s11)
+; CHECK-NEXT:    ld %s40, 4416(, %s11)
+; CHECK-NEXT:    ld %s41, 4408(, %s11)
+; CHECK-NEXT:    ld %s42, 4432(, %s11)
+; CHECK-NEXT:    ld %s43, 4424(, %s11)
+; CHECK-NEXT:    ld %s44, 4448(, %s11)
+; CHECK-NEXT:    ld %s45, 4440(, %s11)
+; CHECK-NEXT:    ld %s46, 4464(, %s11)
+; CHECK-NEXT:    ld %s47, 4456(, %s11)
+; CHECK-NEXT:    ld %s48, 4480(, %s11)
+; CHECK-NEXT:    ld %s49, 4472(, %s11)
+; CHECK-NEXT:    ld %s50, 4496(, %s11)
+; CHECK-NEXT:    ld %s51, 4488(, %s11)
+; CHECK-NEXT:    ld %s52, 4512(, %s11)
+; CHECK-NEXT:    ld %s53, 4504(, %s11)
+; CHECK-NEXT:    ld %s54, 4528(, %s11)
+; CHECK-NEXT:    ld %s55, 4520(, %s11)
+; CHECK-NEXT:    ld %s56, 4280(, %s11)
+; CHECK-NEXT:    ld %s57, 4544(, %s11)
+; CHECK-NEXT:    ld %s58, 4288(, %s11)
+; CHECK-NEXT:    ld %s59, 4536(, %s11)
+; CHECK-NEXT:    ld %s60, 4296(, %s11)
 ; CHECK-NEXT:    and %s57, 1, %s57
-; CHECK-NEXT:    or %s57, %s57, %s58
+; CHECK-NEXT:    st1b %s57, 138(, %s0)
+; CHECK-NEXT:    srl %s57, %s59, 48
+; CHECK-NEXT:    st2b %s57, 136(, %s0)
+; CHECK-NEXT:    sll %s57, %s60, 1
+; CHECK-NEXT:    and %s58, 1, %s58
+; CHECK-NEXT:    or %s57, %s58, %s57
 ; CHECK-NEXT:    st %s57, 8(, %s0)
-; CHECK-NEXT:    srl %s57, %s56, 49
-; CHECK-NEXT:    and %s55, 1, %s55
-; CHECK-NEXT:    sll %s55, %s55, 15
-; CHECK-NEXT:    or %s55, %s57, %s55
-; CHECK-NEXT:    sll %s57, %s60, 16
-; CHECK-NEXT:    or %s55, %s55, %s57
-; CHECK-NEXT:    st %s55, 128(, %s0)
-; CHECK-NEXT:    srl %s55, %s54, 50
-; CHECK-NEXT:    and %s53, 1, %s53
-; CHECK-NEXT:    sll %s53, %s53, 14
-; CHECK-NEXT:    or %s53, %s53, %s55
-; CHECK-NEXT:    sll %s55, %s56, 15
-; CHECK-NEXT:    or %s53, %s53, %s55
-; CHECK-NEXT:    st %s53, 120(, %s0)
-; CHECK-NEXT:    srl %s53, %s52, 51
-; CHECK-NEXT:    and %s51, 1, %s51
-; CHECK-NEXT:    sll %s51, %s51, 13
-; CHECK-NEXT:    or %s51, %s53, %s51
-; CHECK-NEXT:    sll %s53, %s54, 14
-; CHECK-NEXT:    or %s51, %s51, %s53
-; CHECK-NEXT:    st %s51, 112(, %s0)
-; CHECK-NEXT:    srl %s51, %s50, 52
-; CHECK-NEXT:    and %s49, 1, %s49
-; CHECK-NEXT:    sll %s49, %s49, 12
-; CHECK-NEXT:    or %s49, %s49, %s51
-; CHECK-NEXT:    sll %s51, %s52, 13
-; CHECK-NEXT:    or %s49, %s49, %s51
-; CHECK-NEXT:    st %s49, 104(, %s0)
-; CHECK-NEXT:    srl %s49, %s48, 53
-; CHECK-NEXT:    and %s47, 1, %s47
-; CHECK-NEXT:    sll %s47, %s47, 11
-; CHECK-NEXT:    or %s47, %s49, %s47
-; CHECK-NEXT:    sll %s49, %s50, 12
-; CHECK-NEXT:    or %s47, %s47, %s49
-; CHECK-NEXT:    st %s47, 96(, %s0)
-; CHECK-NEXT:    srl %s47, %s46, 54
-; CHECK-NEXT:    and %s45, 1, %s45
-; CHECK-NEXT:    sll %s45, %s45, 10
-; CHECK-NEXT:    or %s45, %s45, %s47
-; CHECK-NEXT:    sll %s47, %s48, 11
-; CHECK-NEXT:    or %s45, %s45, %s47
-; CHECK-NEXT:    st %s45, 88(, %s0)
-; CHECK-NEXT:    srl %s45, %s44, 55
-; CHECK-NEXT:    and %s43, 1, %s43
-; CHECK-NEXT:    sll %s43, %s43, 9
-; CHECK-NEXT:    or %s43, %s45, %s43
-; CHECK-NEXT:    sll %s45, %s46, 10
-; CHECK-NEXT:    or %s43, %s43, %s45
-; CHECK-NEXT:    st %s43, 80(, %s0)
-; CHECK-NEXT:    srl %s43, %s42, 56
-; CHECK-NEXT:    and %s41, 1, %s41
-; CHECK-NEXT:    sll %s41, %s41, 8
-; CHECK-NEXT:    or %s41, %s41, %s43
-; CHECK-NEXT:    sll %s43, %s44, 9
-; CHECK-NEXT:    or %s41, %s41, %s43
-; CHECK-NEXT:    st %s41, 72(, %s0)
-; CHECK-NEXT:    srl %s41, %s40, 57
-; CHECK-NEXT:    and %s39, 1, %s39
-; CHECK-NEXT:    sll %s39, %s39, 7
-; CHECK-NEXT:    or %s39, %s41, %s39
-; CHECK-NEXT:    sll %s41, %s42, 8
-; CHECK-NEXT:    or %s39, %s39, %s41
-; CHECK-NEXT:    st %s39, 64(, %s0)
-; CHECK-NEXT:    srl %s39, %s36, 58
+; CHECK-NEXT:    st %s56, (, %s0)
+; CHECK-NEXT:    srl %s56, %s55, 49
+; CHECK-NEXT:    and %s54, 1, %s54
+; CHECK-NEXT:    sll %s54, %s54, 15
+; CHECK-NEXT:    or %s54, %s56, %s54
+; CHECK-NEXT:    sll %s56, %s59, 16
+; CHECK-NEXT:    or %s54, %s54, %s56
+; CHECK-NEXT:    st %s54, 128(, %s0)
+; CHECK-NEXT:    srl %s54, %s53, 50
+; CHECK-NEXT:    and %s52, 1, %s52
+; CHECK-NEXT:    sll %s52, %s52, 14
+; CHECK-NEXT:    or %s52, %s52, %s54
+; CHECK-NEXT:    sll %s54, %s55, 15
+; CHECK-NEXT:    or %s52, %s52, %s54
+; CHECK-NEXT:    st %s52, 120(, %s0)
+; CHECK-NEXT:    srl %s52, %s51, 51
+; CHECK-NEXT:    and %s50, 1, %s50
+; CHECK-NEXT:    sll %s50, %s50, 13
+; CHECK-NEXT:    or %s50, %s52, %s50
+; CHECK-NEXT:    sll %s52, %s53, 14
+; CHECK-NEXT:    or %s50, %s50, %s52
+; CHECK-NEXT:    st %s50, 112(, %s0)
+; CHECK-NEXT:    srl %s50, %s49, 52
+; CHECK-NEXT:    and %s48, 1, %s48
+; CHECK-NEXT:    sll %s48, %s48, 12
+; CHECK-NEXT:    or %s48, %s48, %s50
+; CHECK-NEXT:    sll %s50, %s51, 13
+; CHECK-NEXT:    or %s48, %s48, %s50
+; CHECK-NEXT:    st %s48, 104(, %s0)
+; CHECK-NEXT:    srl %s48, %s47, 53
+; CHECK-NEXT:    and %s46, 1, %s46
+; CHECK-NEXT:    sll %s46, %s46, 11
+; CHECK-NEXT:    or %s46, %s48, %s46
+; CHECK-NEXT:    sll %s48, %s49, 12
+; CHECK-NEXT:    or %s46, %s46, %s48
+; CHECK-NEXT:    st %s46, 96(, %s0)
+; CHECK-NEXT:    srl %s46, %s45, 54
+; CHECK-NEXT:    and %s44, 1, %s44
+; CHECK-NEXT:    sll %s44, %s44, 10
+; CHECK-NEXT:    or %s44, %s44, %s46
+; CHECK-NEXT:    sll %s46, %s47, 11
+; CHECK-NEXT:    or %s44, %s44, %s46
+; CHECK-NEXT:    st %s44, 88(, %s0)
+; CHECK-NEXT:    srl %s44, %s43, 55
+; CHECK-NEXT:    and %s42, 1, %s42
+; CHECK-NEXT:    sll %s42, %s42, 9
+; CHECK-NEXT:    or %s42, %s44, %s42
+; CHECK-NEXT:    sll %s44, %s45, 10
+; CHECK-NEXT:    or %s42, %s42, %s44
+; CHECK-NEXT:    st %s42, 80(, %s0)
+; CHECK-NEXT:    srl %s42, %s41, 56
+; CHECK-NEXT:    and %s40, 1, %s40
+; CHECK-NEXT:    sll %s40, %s40, 8
+; CHECK-NEXT:    or %s40, %s40, %s42
+; CHECK-NEXT:    sll %s42, %s43, 9
+; CHECK-NEXT:    or %s40, %s40, %s42
+; CHECK-NEXT:    st %s40, 72(, %s0)
+; CHECK-NEXT:    srl %s40, %s39, 57
 ; CHECK-NEXT:    and %s38, 1, %s38
-; CHECK-NEXT:    sll %s38, %s38, 6
-; CHECK-NEXT:    or %s38, %s38, %s39
-; CHECK-NEXT:    sll %s39, %s40, 7
-; CHECK-NEXT:    or %s38, %s38, %s39
-; CHECK-NEXT:    st %s38, 56(, %s0)
-; CHECK-NEXT:    srl %s38, %s34, 59
+; CHECK-NEXT:    sll %s38, %s38, 7
+; CHECK-NEXT:    or %s38, %s40, %s38
+; CHECK-NEXT:    sll %s40, %s41, 8
+; CHECK-NEXT:    or %s38, %s38, %s40
+; CHECK-NEXT:    st %s38, 64(, %s0)
+; CHECK-NEXT:    srl %s38, %s36, 58
+; CHECK-NEXT:    and %s37, 1, %s37
+; CHECK-NEXT:    sll %s37, %s37, 6
+; CHECK-NEXT:    or %s37, %s37, %s38
+; CHECK-NEXT:    sll %s38, %s39, 7
+; CHECK-NEXT:    or %s37, %s37, %s38
+; CHECK-NEXT:    st %s37, 56(, %s0)
+; CHECK-NEXT:    srl %s37, %s34, 59
 ; CHECK-NEXT:    and %s35, 1, %s35
 ; CHECK-NEXT:    sll %s35, %s35, 5
-; CHECK-NEXT:    or %s35, %s38, %s35
+; CHECK-NEXT:    or %s35, %s37, %s35
 ; CHECK-NEXT:    sll %s36, %s36, 6
 ; CHECK-NEXT:    or %s35, %s35, %s36
 ; CHECK-NEXT:    st %s35, 48(, %s0)
@@ -439,7 +439,7 @@ define fastcc <17 x i65> @vreg_arg_v17i65_r1(<256 x i65> %p0, <17 x i65> %p1) {
 ; CHECK-NEXT:    sll %s4, %s4, 3
 ; CHECK-NEXT:    or %s3, %s3, %s4
 ; CHECK-NEXT:    st %s3, 24(, %s0)
-; CHECK-NEXT:    srl %s3, %s37, 63
+; CHECK-NEXT:    srl %s3, %s60, 63
 ; CHECK-NEXT:    and %s2, 1, %s2
 ; CHECK-NEXT:    sll %s2, %s2, 1
 ; CHECK-NEXT:    or %s2, %s3, %s2