Skip to content

Commit 64838ba

Browse files
committed
[AMDGPU] Use GenericTable to classify DGEMM
Since there is a table introduced for MAI instructions extend it to use for DGEMM classification. Differential Revision: https://reviews.llvm.org/D122337
1 parent cad9de7 commit 64838ba

File tree

4 files changed

+15
-7
lines changed

4 files changed

+15
-7
lines changed

llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp

Lines changed: 1 addition & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -116,12 +116,7 @@ static bool isSMovRel(unsigned Opcode) {
116116
}
117117

118118
static bool isDGEMM(unsigned Opcode) {
119-
return Opcode == AMDGPU::V_MFMA_F64_4X4X4F64_e64 ||
120-
Opcode == AMDGPU::V_MFMA_F64_4X4X4F64_vgprcd_e64 ||
121-
Opcode == AMDGPU::V_MFMA_F64_16X16X4F64_e64 ||
122-
Opcode == AMDGPU::V_MFMA_F64_16X16X4F64_vgprcd_e64 ||
123-
Opcode == AMDGPU::V_MFMA_F64_16X16X4F64_mac_e64 ||
124-
Opcode == AMDGPU::V_MFMA_F64_16X16X4F64_mac_vgprcd_e64;
119+
return AMDGPU::getMAIIsDGEMM(Opcode);
125120
}
126121

127122
static bool isXDL(const GCNSubtarget &ST, const MachineInstr &MI) {

llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -343,6 +343,11 @@ bool getVOP3IsSingle(unsigned Opc) {
343343
return Info ? Info->IsSingle : false;
344344
}
345345

346+
bool getMAIIsDGEMM(unsigned Opc) {
347+
const MAIInstInfo *Info = getMAIInstInfoHelper(Opc);
348+
return Info ? Info->is_dgemm : false;
349+
}
350+
346351
bool getMAIIsGFX940XDL(unsigned Opc) {
347352
const MAIInstInfo *Info = getMAIInstInfoHelper(Opc);
348353
return Info ? Info->is_gfx940_xdl : false;

llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -70,6 +70,7 @@ struct GcnBufferFormatInfo {
7070

7171
struct MAIInstInfo {
7272
uint16_t Opcode;
73+
bool is_dgemm;
7374
bool is_gfx940_xdl;
7475
};
7576

@@ -450,6 +451,10 @@ bool getVOP2IsSingle(unsigned Opc);
450451
LLVM_READONLY
451452
bool getVOP3IsSingle(unsigned Opc);
452453

454+
/// Returns true if MAI operation is a double precision GEMM.
455+
LLVM_READONLY
456+
bool getMAIIsDGEMM(unsigned Opc);
457+
453458
LLVM_READONLY
454459
bool getMAIIsGFX940XDL(unsigned Opc);
455460

llvm/lib/Target/AMDGPU/VOP3PInstructions.td

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -487,6 +487,7 @@ let isAsCheapAsAMove = 1, isReMaterializable = 1 in {
487487
class MAIInst<string OpName, VOPProfile P, SDPatternOperator node>
488488
: VOP3InstBase<OpName, P, node> {
489489
Instruction Opcode = !cast<Instruction>(NAME);
490+
bit is_dgemm = 0;
490491
bit is_gfx940_xdl = 0;
491492
}
492493

@@ -559,8 +560,10 @@ let Predicates = [isGFX90APlus] in {
559560
defm V_MFMA_F32_16X16X16BF16_1K : MAIInst<"v_mfma_f32_16x16x16bf16_1k", "F32_V4I16_X4", int_amdgcn_mfma_f32_16x16x16bf16_1k>;
560561
}
561562

563+
let is_dgemm = 1 in {
562564
defm V_MFMA_F64_16X16X4F64 : MAIInst<"v_mfma_f64_16x16x4f64", "F64_16X16X4F64", int_amdgcn_mfma_f64_16x16x4f64>;
563565
defm V_MFMA_F64_4X4X4F64 : MAIInst<"v_mfma_f64_4x4x4f64", "F64_4X4X4F64", int_amdgcn_mfma_f64_4x4x4f64>;
566+
}
564567
} // End Predicates = [isGFX90APlus]
565568

566569
let Predicates = [isGFX940Plus], is_gfx940_xdl = 1 in {
@@ -590,7 +593,7 @@ def MAIInstInfoTable : GenericTable {
590593
let FilterClass = "MAIInst";
591594
let CppTypeName = "MAIInstInfo";
592595
let Fields = [
593-
"Opcode", "is_gfx940_xdl"
596+
"Opcode", "is_dgemm", "is_gfx940_xdl"
594597
];
595598

596599
let PrimaryKey = ["Opcode"];

0 commit comments

Comments
 (0)