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Simon Moll
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[VE] SHL,SRA,SRL v256i32|64 isel and tests
Reviewed By: kaz7 Differential Revision: https://reviews.llvm.org/D115734
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-39
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9 files changed

+205
-39
lines changed

‎llvm/lib/Target/VE/VEISelLowering.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1720,7 +1720,7 @@ SDValue VETargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
17201720
case ISD::EXTRACT_VECTOR_ELT:
17211721
return lowerEXTRACT_VECTOR_ELT(Op, DAG);
17221722

1723-
#define ADD_BINARY_VVP_OP(VVP_NAME, ISD_NAME) case ISD::ISD_NAME:
1723+
#define ADD_BINARY_VVP_OP(VVP_NAME, VP_NAME, ISD_NAME) case ISD::ISD_NAME:
17241724
#include "VVPNodes.def"
17251725
return lowerToVVP(Op, DAG);
17261726
}

‎llvm/lib/Target/VE/VVPInstrInfo.td

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -54,4 +54,8 @@ def c_vvp_or : vvp_commutative<vvp_or>;
5454
def vvp_xor : SDNode<"VEISD::VVP_XOR", SDTIntBinOpVVP>;
5555
def c_vvp_xor : vvp_commutative<vvp_xor>;
5656

57+
def vvp_srl : SDNode<"VEISD::VVP_SRL", SDTIntBinOpVVP>;
58+
def vvp_sra : SDNode<"VEISD::VVP_SRA", SDTIntBinOpVVP>;
59+
def vvp_shl : SDNode<"VEISD::VVP_SHL", SDTIntBinOpVVP>;
60+
5761
// } Binary Operators

‎llvm/lib/Target/VE/VVPInstrPatternsVec.td

Lines changed: 50 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -39,6 +39,28 @@ multiclass Binary_rv<SDPatternOperator OpNode,
3939
ScalarVT:$sx, $vy, $mask, $avl)>;
4040
}
4141

42+
multiclass Binary_vr<SDPatternOperator OpNode,
43+
ValueType ScalarVT, ValueType DataVT,
44+
ValueType MaskVT, string OpBaseName> {
45+
// Masked with select, broadcast.
46+
// TODO
47+
48+
// Unmasked, broadcast.
49+
def : Pat<(OpNode
50+
DataVT:$vx, (any_broadcast ScalarVT:$sy),
51+
(MaskVT true_mask),
52+
i32:$avl),
53+
(!cast<Instruction>(OpBaseName#"vrl")
54+
$vx, ScalarVT:$sy, $avl)>;
55+
// Masked, broadcast.
56+
def : Pat<(OpNode
57+
DataVT:$vx, (any_broadcast ScalarVT:$sy),
58+
MaskVT:$mask,
59+
i32:$avl),
60+
(!cast<Instruction>(OpBaseName#"vrml")
61+
$vx, ScalarVT:$sy, $mask, $avl)>;
62+
}
63+
4264
multiclass Binary_vv<SDPatternOperator OpNode,
4365
ValueType DataVT,
4466
ValueType MaskVT, string OpBaseName> {
@@ -70,6 +92,14 @@ multiclass Binary_rv_vv<
7092
defm : Binary_vv<OpNode, DataVT, MaskVT, OpBaseName>;
7193
}
7294

95+
multiclass Binary_vr_vv<
96+
SDPatternOperator OpNode,
97+
ValueType ScalarVT, ValueType DataVT, ValueType MaskVT,
98+
string OpBaseName> {
99+
defm : Binary_vr<OpNode, ScalarVT, DataVT, MaskVT, OpBaseName>;
100+
defm : Binary_vv<OpNode, DataVT, MaskVT, OpBaseName>;
101+
}
102+
73103
// Expand both 64bit and 32 bit variant (256 elements)
74104
multiclass Binary_rv_vv_ShortLong<
75105
SDPatternOperator OpNode,
@@ -83,6 +113,17 @@ multiclass Binary_rv_vv_ShortLong<
83113
ShortOpBaseName>;
84114
}
85115

116+
multiclass Binary_vr_vv_ShortLong<
117+
SDPatternOperator OpNode,
118+
ValueType LongScalarVT, ValueType LongDataVT, string LongOpBaseName,
119+
ValueType ShortScalarVT, ValueType ShortDataVT, string ShortOpBaseName> {
120+
defm : Binary_vr_vv<OpNode,
121+
LongScalarVT, LongDataVT, v256i1,
122+
LongOpBaseName>;
123+
defm : Binary_vr_vv<OpNode,
124+
ShortScalarVT, ShortDataVT, v256i1,
125+
ShortOpBaseName>;
126+
}
86127

87128
defm : Binary_rv_vv_ShortLong<c_vvp_add,
88129
i64, v256i64, "VADDSL",
@@ -102,3 +143,12 @@ defm : Binary_rv_vv_ShortLong<c_vvp_or,
102143
defm : Binary_rv_vv_ShortLong<c_vvp_xor,
103144
i64, v256i64, "VXOR",
104145
i32, v256i32, "PVXORLO">;
146+
defm : Binary_vr_vv_ShortLong<vvp_shl,
147+
i64, v256i64, "VSLL",
148+
i32, v256i32, "PVSLLLO">;
149+
defm : Binary_vr_vv_ShortLong<vvp_sra,
150+
i64, v256i64, "VSRAL",
151+
i32, v256i32, "PVSRALO">;
152+
defm : Binary_vr_vv_ShortLong<vvp_srl,
153+
i64, v256i64, "VSRL",
154+
i32, v256i32, "PVSRLLO">;

‎llvm/lib/Target/VE/VVPNodes.def

Lines changed: 20 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -28,18 +28,30 @@
2828
/// \p VVPName is a VVP Binary operator.
2929
/// \p SDNAME is the generic SD opcode corresponding to \p VVPName.
3030
#ifndef ADD_BINARY_VVP_OP
31-
#define ADD_BINARY_VVP_OP(X,Y) ADD_VVP_OP(X,Y) HANDLE_VP_TO_VVP(VP_##Y, X)
31+
#define ADD_BINARY_VVP_OP(VVPNAME,VPNAME,SDNAME) \
32+
ADD_VVP_OP(VVPNAME,SDNAME) \
33+
HANDLE_VP_TO_VVP(VPNAME, VVPNAME)
34+
#endif
35+
36+
#ifndef ADD_BINARY_VVP_OP_COMPACT
37+
#define ADD_BINARY_VVP_OP_COMPACT(NAME) \
38+
ADD_BINARY_VVP_OP(VVP_##NAME,VP_##NAME,NAME)
3239
#endif
3340

3441
// Integer arithmetic.
35-
ADD_BINARY_VVP_OP(VVP_ADD,ADD)
36-
ADD_BINARY_VVP_OP(VVP_SUB,SUB)
37-
ADD_BINARY_VVP_OP(VVP_MUL,MUL)
42+
ADD_BINARY_VVP_OP_COMPACT(ADD)
43+
ADD_BINARY_VVP_OP_COMPACT(SUB)
44+
ADD_BINARY_VVP_OP_COMPACT(MUL)
3845

39-
ADD_BINARY_VVP_OP(VVP_AND,AND)
40-
ADD_BINARY_VVP_OP(VVP_OR,OR)
41-
ADD_BINARY_VVP_OP(VVP_XOR,XOR)
46+
ADD_BINARY_VVP_OP(VVP_SRA,VP_ASHR,SRA)
47+
ADD_BINARY_VVP_OP(VVP_SRL,VP_LSHR,SRL)
48+
ADD_BINARY_VVP_OP_COMPACT(SHL)
49+
50+
ADD_BINARY_VVP_OP_COMPACT(AND)
51+
ADD_BINARY_VVP_OP_COMPACT(OR)
52+
ADD_BINARY_VVP_OP_COMPACT(XOR)
4253

43-
#undef HANDLE_VP_TO_VVP
4454
#undef ADD_BINARY_VVP_OP
55+
#undef ADD_BINARY_VVP_OP_COMPACT
4556
#undef ADD_VVP_OP
57+
#undef HANDLE_VP_TO_VVP

‎llvm/test/CodeGen/VE/Vector/vp_ashr.ll

Lines changed: 23 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1,16 +1,29 @@
1-
; REQUIRES: asserts
2-
; RUN: not --crash llc < %s -march=ve -mattr=+vpu -o /dev/null 2>&1 | FileCheck %s
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2+
; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
33

4-
; CHECK: t{{[0-9]+}}: v256i32 = vp_ashr [[A:t[0-9]+]], [[B:t[0-9]+]], [[MASK:t[0-9]+]], [[EVL:t[0-9]+]]
5-
; CHECK: [[A]]: v256i32
6-
; CHECK: [[B]]: v256i32
7-
; CHECK: [[MASK]]: v256i1
8-
; CHECK: [[EVL]]: i32
4+
declare <256 x i32> @llvm.vp.ashr.v256i32(<256 x i32>, <256 x i32>, <256 x i1>, i32)
95

10-
define <256 x i32> @test_vp_int(<256 x i32> %i0, <256 x i32> %i1, <256 x i1> %m, i32 %n) {
6+
define fastcc <256 x i32> @test_vp_int(<256 x i32> %i0, <256 x i32> %i1, <256 x i1> %m, i32 %n) {
7+
; CHECK-LABEL: test_vp_int:
8+
; CHECK: # %bb.0:
9+
; CHECK-NEXT: and %s0, %s0, (32)0
10+
; CHECK-NEXT: lvl %s0
11+
; CHECK-NEXT: pvsra.lo %v0, %v0, %v1, %vm1
12+
; CHECK-NEXT: b.l.t (, %s10)
1113
%r0 = call <256 x i32> @llvm.vp.ashr.v256i32(<256 x i32> %i0, <256 x i32> %i1, <256 x i1> %m, i32 %n)
1214
ret <256 x i32> %r0
1315
}
1416

15-
; integer arith
16-
declare <256 x i32> @llvm.vp.ashr.v256i32(<256 x i32>, <256 x i32>, <256 x i1>, i32)
17+
18+
declare <256 x i64> @llvm.vp.ashr.v256i64(<256 x i64>, <256 x i64>, <256 x i1>, i32)
19+
20+
define fastcc <256 x i64> @test_vp_v256i64(<256 x i64> %i0, <256 x i64> %i1, <256 x i1> %m, i32 %n) {
21+
; CHECK-LABEL: test_vp_v256i64:
22+
; CHECK: # %bb.0:
23+
; CHECK-NEXT: and %s0, %s0, (32)0
24+
; CHECK-NEXT: lvl %s0
25+
; CHECK-NEXT: vsra.l %v0, %v0, %v1, %vm1
26+
; CHECK-NEXT: b.l.t (, %s10)
27+
%r0 = call <256 x i64> @llvm.vp.ashr.v256i64(<256 x i64> %i0, <256 x i64> %i1, <256 x i1> %m, i32 %n)
28+
ret <256 x i64> %r0
29+
}

‎llvm/test/CodeGen/VE/Vector/vp_lshr.ll

Lines changed: 24 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1,16 +1,30 @@
1-
; REQUIRES: asserts
2-
; RUN: not --crash llc < %s -march=ve -mattr=+vpu -o /dev/null 2>&1 | FileCheck %s
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2+
; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
33

4-
; CHECK: t{{[0-9]+}}: v256i32 = vp_lshr [[A:t[0-9]+]], [[B:t[0-9]+]], [[MASK:t[0-9]+]], [[EVL:t[0-9]+]]
5-
; CHECK: [[A]]: v256i32
6-
; CHECK: [[B]]: v256i32
7-
; CHECK: [[MASK]]: v256i1
8-
; CHECK: [[EVL]]: i32
4+
declare <256 x i32> @llvm.vp.lshr.v256i32(<256 x i32>, <256 x i32>, <256 x i1>, i32)
95

10-
define <256 x i32> @test_vp_int(<256 x i32> %i0, <256 x i32> %i1, <256 x i1> %m, i32 %n) {
6+
define fastcc <256 x i32> @test_vp_int(<256 x i32> %i0, <256 x i32> %i1, <256 x i1> %m, i32 %n) {
7+
; CHECK-LABEL: test_vp_int:
8+
; CHECK: # %bb.0:
9+
; CHECK-NEXT: and %s0, %s0, (32)0
10+
; CHECK-NEXT: lvl %s0
11+
; CHECK-NEXT: pvsrl.lo %v0, %v0, %v1, %vm1
12+
; CHECK-NEXT: b.l.t (, %s10)
1113
%r0 = call <256 x i32> @llvm.vp.lshr.v256i32(<256 x i32> %i0, <256 x i32> %i1, <256 x i1> %m, i32 %n)
1214
ret <256 x i32> %r0
1315
}
1416

15-
; integer arith
16-
declare <256 x i32> @llvm.vp.lshr.v256i32(<256 x i32>, <256 x i32>, <256 x i1>, i32)
17+
18+
declare <256 x i64> @llvm.vp.lshr.v256i64(<256 x i64>, <256 x i64>, <256 x i1>, i32)
19+
20+
define fastcc <256 x i64> @test_vp_v256i64(<256 x i64> %i0, <256 x i64> %i1, <256 x i1> %m, i32 %n) {
21+
; CHECK-LABEL: test_vp_v256i64:
22+
; CHECK: # %bb.0:
23+
; CHECK-NEXT: and %s0, %s0, (32)0
24+
; CHECK-NEXT: lvl %s0
25+
; CHECK-NEXT: vsrl %v0, %v0, %v1, %vm1
26+
; CHECK-NEXT: b.l.t (, %s10)
27+
%r0 = call <256 x i64> @llvm.vp.lshr.v256i64(<256 x i64> %i0, <256 x i64> %i1, <256 x i1> %m, i32 %n)
28+
ret <256 x i64> %r0
29+
}
30+

‎llvm/test/CodeGen/VE/Vector/vp_shl.ll

Lines changed: 23 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1,16 +1,29 @@
1-
; REQUIRES: asserts
2-
; RUN: not --crash llc < %s -march=ve -mattr=+vpu -o /dev/null 2>&1 | FileCheck %s
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2+
; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
33

4-
; CHECK: t{{[0-9]+}}: v256i32 = vp_shl [[A:t[0-9]+]], [[B:t[0-9]+]], [[MASK:t[0-9]+]], [[EVL:t[0-9]+]]
5-
; CHECK: [[A]]: v256i32
6-
; CHECK: [[B]]: v256i32
7-
; CHECK: [[MASK]]: v256i1
8-
; CHECK: [[EVL]]: i32
4+
declare <256 x i32> @llvm.vp.shl.v256i32(<256 x i32>, <256 x i32>, <256 x i1>, i32)
95

10-
define <256 x i32> @test_vp_int(<256 x i32> %i0, <256 x i32> %i1, <256 x i1> %m, i32 %n) {
6+
define fastcc <256 x i32> @test_vp_v256i32(<256 x i32> %i0, <256 x i32> %i1, <256 x i1> %m, i32 %n) {
7+
; CHECK-LABEL: test_vp_v256i32:
8+
; CHECK: # %bb.0:
9+
; CHECK-NEXT: and %s0, %s0, (32)0
10+
; CHECK-NEXT: lvl %s0
11+
; CHECK-NEXT: pvsll.lo %v0, %v0, %v1, %vm1
12+
; CHECK-NEXT: b.l.t (, %s10)
1113
%r0 = call <256 x i32> @llvm.vp.shl.v256i32(<256 x i32> %i0, <256 x i32> %i1, <256 x i1> %m, i32 %n)
1214
ret <256 x i32> %r0
1315
}
1416

15-
; integer arith
16-
declare <256 x i32> @llvm.vp.shl.v256i32(<256 x i32>, <256 x i32>, <256 x i1>, i32)
17+
18+
declare <256 x i64> @llvm.vp.shl.v256i64(<256 x i64>, <256 x i64>, <256 x i1>, i32)
19+
20+
define fastcc <256 x i64> @test_vp_v256i64(<256 x i64> %i0, <256 x i64> %i1, <256 x i1> %m, i32 %n) {
21+
; CHECK-LABEL: test_vp_v256i64:
22+
; CHECK: # %bb.0:
23+
; CHECK-NEXT: and %s0, %s0, (32)0
24+
; CHECK-NEXT: lvl %s0
25+
; CHECK-NEXT: vsll %v0, %v0, %v1, %vm1
26+
; CHECK-NEXT: b.l.t (, %s10)
27+
%r0 = call <256 x i64> @llvm.vp.shl.v256i64(<256 x i64> %i0, <256 x i64> %i1, <256 x i1> %m, i32 %n)
28+
ret <256 x i64> %r0
29+
}

‎llvm/test/CodeGen/VE/Vector/vp_sra.ll

Lines changed: 30 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,30 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2+
; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
3+
4+
declare <256 x i32> @llvm.vp.ashr.v256i32(<256 x i32>, <256 x i32>, <256 x i1>, i32)
5+
6+
define fastcc <256 x i32> @test_vp_ashr_v256i32(<256 x i32> %i0, <256 x i32> %i1, <256 x i1> %m, i32 %n) {
7+
; CHECK-LABEL: test_vp_ashr_v256i32:
8+
; CHECK: # %bb.0:
9+
; CHECK-NEXT: and %s0, %s0, (32)0
10+
; CHECK-NEXT: lvl %s0
11+
; CHECK-NEXT: pvsra.lo %v0, %v0, %v1, %vm1
12+
; CHECK-NEXT: b.l.t (, %s10)
13+
%r0 = call <256 x i32> @llvm.vp.ashr.v256i32(<256 x i32> %i0, <256 x i32> %i1, <256 x i1> %m, i32 %n)
14+
ret <256 x i32> %r0
15+
}
16+
17+
18+
declare <256 x i64> @llvm.vp.ashr.v256i64(<256 x i64>, <256 x i64>, <256 x i1>, i32)
19+
20+
define fastcc <256 x i64> @test_vp_int_v256i64(<256 x i64> %i0, <256 x i64> %i1, <256 x i1> %m, i32 %n) {
21+
; CHECK-LABEL: test_vp_int_v256i64:
22+
; CHECK: # %bb.0:
23+
; CHECK-NEXT: and %s0, %s0, (32)0
24+
; CHECK-NEXT: lvl %s0
25+
; CHECK-NEXT: vsra.l %v0, %v0, %v1, %vm1
26+
; CHECK-NEXT: b.l.t (, %s10)
27+
%r0 = call <256 x i64> @llvm.vp.ashr.v256i64(<256 x i64> %i0, <256 x i64> %i1, <256 x i1> %m, i32 %n)
28+
ret <256 x i64> %r0
29+
}
30+

‎llvm/test/CodeGen/VE/Vector/vp_srl.ll

Lines changed: 30 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,30 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2+
; RUN: llc < %s -march=ve -mattr=+vpu | FileCheck %s
3+
4+
declare <256 x i32> @llvm.vp.lshr.v256i32(<256 x i32>, <256 x i32>, <256 x i1>, i32)
5+
6+
define fastcc <256 x i32> @test_vp_lshr_v256i32(<256 x i32> %i0, <256 x i32> %i1, <256 x i1> %m, i32 %n) {
7+
; CHECK-LABEL: test_vp_lshr_v256i32:
8+
; CHECK: # %bb.0:
9+
; CHECK-NEXT: and %s0, %s0, (32)0
10+
; CHECK-NEXT: lvl %s0
11+
; CHECK-NEXT: pvsrl.lo %v0, %v0, %v1, %vm1
12+
; CHECK-NEXT: b.l.t (, %s10)
13+
%r0 = call <256 x i32> @llvm.vp.lshr.v256i32(<256 x i32> %i0, <256 x i32> %i1, <256 x i1> %m, i32 %n)
14+
ret <256 x i32> %r0
15+
}
16+
17+
18+
declare <256 x i64> @llvm.vp.lshr.v256i64(<256 x i64>, <256 x i64>, <256 x i1>, i32)
19+
20+
define fastcc <256 x i64> @test_vp_int_v256i64(<256 x i64> %i0, <256 x i64> %i1, <256 x i1> %m, i32 %n) {
21+
; CHECK-LABEL: test_vp_int_v256i64:
22+
; CHECK: # %bb.0:
23+
; CHECK-NEXT: and %s0, %s0, (32)0
24+
; CHECK-NEXT: lvl %s0
25+
; CHECK-NEXT: vsrl %v0, %v0, %v1, %vm1
26+
; CHECK-NEXT: b.l.t (, %s10)
27+
%r0 = call <256 x i64> @llvm.vp.lshr.v256i64(<256 x i64> %i0, <256 x i64> %i1, <256 x i1> %m, i32 %n)
28+
ret <256 x i64> %r0
29+
}
30+

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