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[RISCV] Precommit tests for override hasAndNotCompare.
Precommit tests for D115922. Differential Revision: https://reviews.llvm.org/D116013
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‎llvm/test/CodeGen/RISCV/rv32zbb-zbp.ll

Lines changed: 114 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -557,3 +557,117 @@ define i16 @srai_i16(i16 %a) nounwind {
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%1 = ashr i16 %a, 9
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ret i16 %1
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}
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define i1 @andn_seqz_i32(i32 %a, i32 %b) nounwind {
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; RV32I-LABEL: andn_seqz_i32:
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; RV32I: # %bb.0:
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; RV32I-NEXT: and a0, a0, a1
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; RV32I-NEXT: xor a0, a0, a1
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; RV32I-NEXT: seqz a0, a0
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; RV32I-NEXT: ret
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;
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; RV32ZBB-LABEL: andn_seqz_i32:
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; RV32ZBB: # %bb.0:
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; RV32ZBB-NEXT: and a0, a0, a1
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; RV32ZBB-NEXT: xor a0, a0, a1
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; RV32ZBB-NEXT: seqz a0, a0
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; RV32ZBB-NEXT: ret
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;
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; RV32ZBP-LABEL: andn_seqz_i32:
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; RV32ZBP: # %bb.0:
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; RV32ZBP-NEXT: and a0, a0, a1
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; RV32ZBP-NEXT: xor a0, a0, a1
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; RV32ZBP-NEXT: seqz a0, a0
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; RV32ZBP-NEXT: ret
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%and = and i32 %a, %b
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%cmpeq = icmp eq i32 %and, %b
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ret i1 %cmpeq
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}
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define i1 @andn_seqz_i64(i64 %a, i64 %b) nounwind {
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; RV32I-LABEL: andn_seqz_i64:
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; RV32I: # %bb.0:
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; RV32I-NEXT: not a0, a0
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; RV32I-NEXT: not a1, a1
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; RV32I-NEXT: and a1, a1, a3
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; RV32I-NEXT: and a0, a0, a2
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; RV32I-NEXT: or a0, a0, a1
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; RV32I-NEXT: seqz a0, a0
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; RV32I-NEXT: ret
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;
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; RV32ZBB-LABEL: andn_seqz_i64:
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; RV32ZBB: # %bb.0:
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; RV32ZBB-NEXT: andn a1, a3, a1
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; RV32ZBB-NEXT: andn a0, a2, a0
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; RV32ZBB-NEXT: or a0, a0, a1
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; RV32ZBB-NEXT: seqz a0, a0
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; RV32ZBB-NEXT: ret
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;
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; RV32ZBP-LABEL: andn_seqz_i64:
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; RV32ZBP: # %bb.0:
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; RV32ZBP-NEXT: andn a1, a3, a1
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; RV32ZBP-NEXT: andn a0, a2, a0
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; RV32ZBP-NEXT: or a0, a0, a1
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; RV32ZBP-NEXT: seqz a0, a0
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; RV32ZBP-NEXT: ret
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%and = and i64 %a, %b
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%cmpeq = icmp eq i64 %and, %b
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ret i1 %cmpeq
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}
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define i1 @andn_snez_i32(i32 %a, i32 %b) nounwind {
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; RV32I-LABEL: andn_snez_i32:
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; RV32I: # %bb.0:
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; RV32I-NEXT: and a0, a0, a1
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; RV32I-NEXT: xor a0, a0, a1
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; RV32I-NEXT: snez a0, a0
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; RV32I-NEXT: ret
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;
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; RV32ZBB-LABEL: andn_snez_i32:
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; RV32ZBB: # %bb.0:
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; RV32ZBB-NEXT: and a0, a0, a1
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; RV32ZBB-NEXT: xor a0, a0, a1
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; RV32ZBB-NEXT: snez a0, a0
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; RV32ZBB-NEXT: ret
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;
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; RV32ZBP-LABEL: andn_snez_i32:
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; RV32ZBP: # %bb.0:
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; RV32ZBP-NEXT: and a0, a0, a1
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; RV32ZBP-NEXT: xor a0, a0, a1
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; RV32ZBP-NEXT: snez a0, a0
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; RV32ZBP-NEXT: ret
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%and = and i32 %a, %b
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%cmpeq = icmp ne i32 %and, %b
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ret i1 %cmpeq
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}
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define i1 @andn_snez_i64(i64 %a, i64 %b) nounwind {
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; RV32I-LABEL: andn_snez_i64:
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; RV32I: # %bb.0:
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; RV32I-NEXT: not a0, a0
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; RV32I-NEXT: not a1, a1
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; RV32I-NEXT: and a1, a1, a3
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; RV32I-NEXT: and a0, a0, a2
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; RV32I-NEXT: or a0, a0, a1
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; RV32I-NEXT: snez a0, a0
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; RV32I-NEXT: ret
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;
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; RV32ZBB-LABEL: andn_snez_i64:
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; RV32ZBB: # %bb.0:
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; RV32ZBB-NEXT: andn a1, a3, a1
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; RV32ZBB-NEXT: andn a0, a2, a0
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; RV32ZBB-NEXT: or a0, a0, a1
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; RV32ZBB-NEXT: snez a0, a0
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; RV32ZBB-NEXT: ret
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;
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; RV32ZBP-LABEL: andn_snez_i64:
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; RV32ZBP: # %bb.0:
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; RV32ZBP-NEXT: andn a1, a3, a1
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; RV32ZBP-NEXT: andn a0, a2, a0
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; RV32ZBP-NEXT: or a0, a0, a1
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; RV32ZBP-NEXT: snez a0, a0
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; RV32ZBP-NEXT: ret
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%and = and i64 %a, %b
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%cmpeq = icmp ne i64 %and, %b
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ret i1 %cmpeq
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}

‎llvm/test/CodeGen/RISCV/rv64zbb-zbp.ll

Lines changed: 104 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -628,3 +628,107 @@ define i16 @srai_i16(i16 %a) nounwind {
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%1 = ashr i16 %a, 9
629629
ret i16 %1
630630
}
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define i1 @andn_seqz_i32(i32 signext %a, i32 signext %b) nounwind {
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; RV64I-LABEL: andn_seqz_i32:
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; RV64I: # %bb.0:
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; RV64I-NEXT: and a0, a0, a1
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; RV64I-NEXT: xor a0, a0, a1
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; RV64I-NEXT: seqz a0, a0
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; RV64I-NEXT: ret
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;
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; RV64ZBB-LABEL: andn_seqz_i32:
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; RV64ZBB: # %bb.0:
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; RV64ZBB-NEXT: and a0, a0, a1
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; RV64ZBB-NEXT: xor a0, a0, a1
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; RV64ZBB-NEXT: seqz a0, a0
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; RV64ZBB-NEXT: ret
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;
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; RV64ZBP-LABEL: andn_seqz_i32:
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; RV64ZBP: # %bb.0:
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; RV64ZBP-NEXT: and a0, a0, a1
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; RV64ZBP-NEXT: xor a0, a0, a1
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; RV64ZBP-NEXT: seqz a0, a0
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; RV64ZBP-NEXT: ret
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%and = and i32 %a, %b
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%cmpeq = icmp eq i32 %and, %b
655+
ret i1 %cmpeq
656+
}
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define i1 @andn_seqz_i64(i64 %a, i64 %b) nounwind {
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; RV64I-LABEL: andn_seqz_i64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: and a0, a0, a1
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; RV64I-NEXT: xor a0, a0, a1
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; RV64I-NEXT: seqz a0, a0
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; RV64I-NEXT: ret
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;
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; RV64ZBB-LABEL: andn_seqz_i64:
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; RV64ZBB: # %bb.0:
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; RV64ZBB-NEXT: and a0, a0, a1
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; RV64ZBB-NEXT: xor a0, a0, a1
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; RV64ZBB-NEXT: seqz a0, a0
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; RV64ZBB-NEXT: ret
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;
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; RV64ZBP-LABEL: andn_seqz_i64:
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; RV64ZBP: # %bb.0:
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; RV64ZBP-NEXT: and a0, a0, a1
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; RV64ZBP-NEXT: xor a0, a0, a1
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; RV64ZBP-NEXT: seqz a0, a0
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; RV64ZBP-NEXT: ret
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%and = and i64 %a, %b
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%cmpeq = icmp eq i64 %and, %b
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ret i1 %cmpeq
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}
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define i1 @andn_snez_i32(i32 signext %a, i32 signext %b) nounwind {
685+
; RV64I-LABEL: andn_snez_i32:
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; RV64I: # %bb.0:
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; RV64I-NEXT: and a0, a0, a1
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; RV64I-NEXT: xor a0, a0, a1
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; RV64I-NEXT: snez a0, a0
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; RV64I-NEXT: ret
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;
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; RV64ZBB-LABEL: andn_snez_i32:
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; RV64ZBB: # %bb.0:
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; RV64ZBB-NEXT: and a0, a0, a1
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; RV64ZBB-NEXT: xor a0, a0, a1
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; RV64ZBB-NEXT: snez a0, a0
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; RV64ZBB-NEXT: ret
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;
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; RV64ZBP-LABEL: andn_snez_i32:
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; RV64ZBP: # %bb.0:
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; RV64ZBP-NEXT: and a0, a0, a1
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; RV64ZBP-NEXT: xor a0, a0, a1
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; RV64ZBP-NEXT: snez a0, a0
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; RV64ZBP-NEXT: ret
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%and = and i32 %a, %b
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%cmpeq = icmp ne i32 %and, %b
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ret i1 %cmpeq
708+
}
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define i1 @andn_snez_i64(i64 %a, i64 %b) nounwind {
711+
; RV64I-LABEL: andn_snez_i64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: and a0, a0, a1
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; RV64I-NEXT: xor a0, a0, a1
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; RV64I-NEXT: snez a0, a0
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; RV64I-NEXT: ret
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;
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; RV64ZBB-LABEL: andn_snez_i64:
719+
; RV64ZBB: # %bb.0:
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; RV64ZBB-NEXT: and a0, a0, a1
721+
; RV64ZBB-NEXT: xor a0, a0, a1
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; RV64ZBB-NEXT: snez a0, a0
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; RV64ZBB-NEXT: ret
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;
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; RV64ZBP-LABEL: andn_snez_i64:
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; RV64ZBP: # %bb.0:
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; RV64ZBP-NEXT: and a0, a0, a1
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; RV64ZBP-NEXT: xor a0, a0, a1
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; RV64ZBP-NEXT: snez a0, a0
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; RV64ZBP-NEXT: ret
731+
%and = and i64 %a, %b
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%cmpeq = icmp ne i64 %and, %b
733+
ret i1 %cmpeq
734+
}

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