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davemgreendavemgreen
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[AArch64] Add some additional tests for conditions of branches. NFC
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‎llvm/test/CodeGen/AArch64/andorbrcompare.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-none-none-eabi -verify-machineinstrs %s -o - | FileCheck %s
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declare void @dummy()
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define i32 @and_eq_ne_ult(i32 %s0, i32 %s1, i32 %s2, i32 %s3, i32 %s4, i32 %s5, i32* %p) {
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; CHECK-LABEL: and_eq_ne_ult:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cmp w0, w1
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; CHECK-NEXT: ccmp w2, w3, #4, eq
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; CHECK-NEXT: b.ne .LBB0_3
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; CHECK-NEXT: // %bb.1: // %entry
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; CHECK-NEXT: cmp w4, w5
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; CHECK-NEXT: b.lo .LBB0_3
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; CHECK-NEXT: // %bb.2:
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; CHECK-NEXT: mov w0, wzr
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB0_3: // %if
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; CHECK-NEXT: mov w0, #1
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; CHECK-NEXT: str w0, [x6]
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; CHECK-NEXT: ret
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entry:
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%c0 = icmp eq i32 %s0, %s1
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%c1 = icmp ne i32 %s2, %s3
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%a = and i1 %c0, %c1
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%c2 = icmp ult i32 %s4, %s5
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%o = or i1 %a, %c2
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br i1 %o, label %if, label %else
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if:
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store i32 1, i32* %p
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ret i32 1
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else:
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ret i32 0
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}
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define i32 @and_ne_ult_ule(i32 %s0, i32 %s1, i32 %s2, i32 %s3, i32 %s4, i32 %s5, i32* %p) {
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; CHECK-LABEL: and_ne_ult_ule:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cmp w0, w1
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; CHECK-NEXT: ccmp w2, w3, #2, ne
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; CHECK-NEXT: b.lo .LBB1_3
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; CHECK-NEXT: // %bb.1: // %entry
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; CHECK-NEXT: cmp w4, w5
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; CHECK-NEXT: b.ls .LBB1_3
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; CHECK-NEXT: // %bb.2:
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; CHECK-NEXT: mov w0, wzr
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB1_3: // %if
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; CHECK-NEXT: mov w0, #1
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; CHECK-NEXT: str w0, [x6]
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; CHECK-NEXT: ret
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entry:
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%c0 = icmp ne i32 %s0, %s1
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%c1 = icmp ult i32 %s2, %s3
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%a = and i1 %c0, %c1
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%c2 = icmp ule i32 %s4, %s5
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%o = or i1 %a, %c2
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br i1 %o, label %if, label %else
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if:
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store i32 1, i32* %p
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ret i32 1
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else:
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ret i32 0
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}
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define i32 @and_ult_ule_ugt(i32 %s0, i32 %s1, i32 %s2, i32 %s3, i32 %s4, i32 %s5, i32* %p) {
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; CHECK-LABEL: and_ult_ule_ugt:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cmp w0, w1
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; CHECK-NEXT: ccmp w2, w3, #2, lo
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; CHECK-NEXT: b.ls .LBB2_3
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; CHECK-NEXT: // %bb.1: // %entry
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; CHECK-NEXT: cmp w4, w5
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; CHECK-NEXT: b.hi .LBB2_3
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; CHECK-NEXT: // %bb.2:
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; CHECK-NEXT: mov w0, wzr
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB2_3: // %if
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; CHECK-NEXT: mov w0, #1
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; CHECK-NEXT: str w0, [x6]
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; CHECK-NEXT: ret
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entry:
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%c0 = icmp ult i32 %s0, %s1
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%c1 = icmp ule i32 %s2, %s3
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%a = and i1 %c0, %c1
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%c2 = icmp ugt i32 %s4, %s5
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%o = or i1 %a, %c2
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br i1 %o, label %if, label %else
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if:
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store i32 1, i32* %p
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ret i32 1
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else:
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ret i32 0
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}
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define i32 @and_ule_ugt_uge(i32 %s0, i32 %s1, i32 %s2, i32 %s3, i32 %s4, i32 %s5, i32* %p) {
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; CHECK-LABEL: and_ule_ugt_uge:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cmp w0, w1
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; CHECK-NEXT: ccmp w2, w3, #0, ls
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; CHECK-NEXT: b.hi .LBB3_3
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; CHECK-NEXT: // %bb.1: // %entry
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; CHECK-NEXT: cmp w4, w5
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; CHECK-NEXT: b.hs .LBB3_3
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; CHECK-NEXT: // %bb.2:
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; CHECK-NEXT: mov w0, wzr
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB3_3: // %if
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; CHECK-NEXT: mov w0, #1
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; CHECK-NEXT: str w0, [x6]
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; CHECK-NEXT: ret
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entry:
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%c0 = icmp ule i32 %s0, %s1
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%c1 = icmp ugt i32 %s2, %s3
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%a = and i1 %c0, %c1
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%c2 = icmp uge i32 %s4, %s5
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%o = or i1 %a, %c2
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br i1 %o, label %if, label %else
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if:
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store i32 1, i32* %p
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ret i32 1
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else:
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ret i32 0
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}
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define i32 @and_ugt_uge_slt(i32 %s0, i32 %s1, i32 %s2, i32 %s3, i32 %s4, i32 %s5, i32* %p) {
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; CHECK-LABEL: and_ugt_uge_slt:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cmp w0, w1
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; CHECK-NEXT: ccmp w2, w3, #0, hi
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; CHECK-NEXT: b.hs .LBB4_3
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; CHECK-NEXT: // %bb.1: // %entry
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; CHECK-NEXT: cmp w4, w5
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; CHECK-NEXT: b.lt .LBB4_3
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; CHECK-NEXT: // %bb.2:
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; CHECK-NEXT: mov w0, wzr
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB4_3: // %if
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; CHECK-NEXT: mov w0, #1
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; CHECK-NEXT: str w0, [x6]
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; CHECK-NEXT: ret
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entry:
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%c0 = icmp ugt i32 %s0, %s1
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%c1 = icmp uge i32 %s2, %s3
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%a = and i1 %c0, %c1
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%c2 = icmp slt i32 %s4, %s5
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%o = or i1 %a, %c2
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br i1 %o, label %if, label %else
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if:
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store i32 1, i32* %p
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ret i32 1
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else:
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ret i32 0
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}
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define i32 @and_uge_slt_sle(i32 %s0, i32 %s1, i32 %s2, i32 %s3, i32 %s4, i32 %s5, i32* %p) {
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; CHECK-LABEL: and_uge_slt_sle:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cmp w0, w1
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; CHECK-NEXT: ccmp w2, w3, #0, hs
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; CHECK-NEXT: b.lt .LBB5_3
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; CHECK-NEXT: // %bb.1: // %entry
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; CHECK-NEXT: cmp w4, w5
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; CHECK-NEXT: b.le .LBB5_3
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; CHECK-NEXT: // %bb.2:
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; CHECK-NEXT: mov w0, wzr
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB5_3: // %if
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; CHECK-NEXT: mov w0, #1
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; CHECK-NEXT: str w0, [x6]
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; CHECK-NEXT: ret
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entry:
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%c0 = icmp uge i32 %s0, %s1
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%c1 = icmp slt i32 %s2, %s3
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%a = and i1 %c0, %c1
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%c2 = icmp sle i32 %s4, %s5
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%o = or i1 %a, %c2
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br i1 %o, label %if, label %else
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if:
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store i32 1, i32* %p
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ret i32 1
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else:
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ret i32 0
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}
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define i32 @and_slt_sle_sgt(i32 %s0, i32 %s1, i32 %s2, i32 %s3, i32 %s4, i32 %s5, i32* %p) {
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; CHECK-LABEL: and_slt_sle_sgt:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cmp w0, w1
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; CHECK-NEXT: ccmp w2, w3, #0, lt
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; CHECK-NEXT: b.le .LBB6_3
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; CHECK-NEXT: // %bb.1: // %entry
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; CHECK-NEXT: cmp w4, w5
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; CHECK-NEXT: b.gt .LBB6_3
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; CHECK-NEXT: // %bb.2:
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; CHECK-NEXT: mov w0, wzr
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB6_3: // %if
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; CHECK-NEXT: mov w0, #1
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; CHECK-NEXT: str w0, [x6]
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; CHECK-NEXT: ret
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entry:
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%c0 = icmp slt i32 %s0, %s1
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%c1 = icmp sle i32 %s2, %s3
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%a = and i1 %c0, %c1
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%c2 = icmp sgt i32 %s4, %s5
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%o = or i1 %a, %c2
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br i1 %o, label %if, label %else
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if:
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store i32 1, i32* %p
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ret i32 1
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else:
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ret i32 0
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}
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define i32 @and_sle_sgt_sge(i32 %s0, i32 %s1, i32 %s2, i32 %s3, i32 %s4, i32 %s5, i32* %p) {
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; CHECK-LABEL: and_sle_sgt_sge:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cmp w0, w1
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; CHECK-NEXT: ccmp w2, w3, #4, le
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; CHECK-NEXT: b.gt .LBB7_3
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; CHECK-NEXT: // %bb.1: // %entry
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; CHECK-NEXT: cmp w4, w5
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; CHECK-NEXT: b.ge .LBB7_3
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; CHECK-NEXT: // %bb.2:
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; CHECK-NEXT: mov w0, wzr
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB7_3: // %if
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; CHECK-NEXT: mov w0, #1
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; CHECK-NEXT: str w0, [x6]
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; CHECK-NEXT: ret
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entry:
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%c0 = icmp sle i32 %s0, %s1
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%c1 = icmp sgt i32 %s2, %s3
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%a = and i1 %c0, %c1
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%c2 = icmp sge i32 %s4, %s5
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%o = or i1 %a, %c2
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br i1 %o, label %if, label %else
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if:
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store i32 1, i32* %p
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ret i32 1
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else:
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ret i32 0
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}

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