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add: sdc file
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tang20k/scr1/tang20k_scr1.sdc

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//Copyright (C)2014-2025 GOWIN Semiconductor Corporation.
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//All rights reserved.
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//File Title: Timing Constraints file
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//Tool Version: V1.9.10.03 Education
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//Created Time: 2025-02-19 13:51:59
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create_clock -name CLK -period 37.037 -waveform {0 18.518} [get_ports {CLK}] -add
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create_clock -name JTAG_TCK -period 1000 -waveform {0 125} [get_ports {JTAG_TCK}] -add
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set_input_delay -clock JTAG_TCK 6.6 -add_delay [get_ports {JTAG_TMS JTAG_TDI}]
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set_output_delay -clock JTAG_TCK 3.3 -add_delay [get_ports {JTAG_TDO}]

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