@@ -175,7 +175,7 @@ namespace eval _SC_INTERNALS {
175175 return -code error " invalid MXL value: $xlen "
176176 }
177177
178- proc sc_lib_riscv_encode_abstarct_command {regno write transfer aarsize cmdtype} {
178+ proc sc_lib_riscv_encode_abstract_command {regno write transfer aarsize cmdtype} {
179179 set cmd [expr {($regno & 0xFFFF) |
180180 ($write << 16) |
181181 ($transfer << 17) |
@@ -191,29 +191,38 @@ namespace eval _SC_INTERNALS {
191191 }
192192 }
193193
194+ proc sc_lib_require_disabled_background_poll {} {
195+ set poll_output [poll]
196+ if {[string first " background polling: off" $poll_output ] == -1} {
197+ return -code error " background polling must be disabled"
198+ }
199+ }
200+
194201 variable FPGA_LIB_BUSY_DURATION 3
195202
196203 proc sc_lib_riscv_csr_impl {csr_num value write xlen} {
197204 set aarsize [sc_lib_get_aarsize $xlen ]
198205 set COMMAND_ADDR 0x17
199- riscv dmi_write $COMMAND_ADDR [sc_lib_riscv_encode_abstarct_command $csr_num \
206+ riscv dmi_write $COMMAND_ADDR [sc_lib_riscv_encode_abstract_command $csr_num \
200207 $write 1 $aarsize 0]
201208
202209 set ABSTRACTCS_ADDR 0x16
203210 set abstractcs [riscv dmi_read $ABSTRACTCS_ADDR ]
204211 set start_time [clock seconds]
205212
213+ set max_busy_duration [sc_fpga_get_busy_duration]
206214 while {$abstractcs & 0x1000 != 0} {
207- if {([clock seconds] - $start_time ) >= [sc_fpga_get_busy_duration]} {
208- return -code error " Busy bit set after duration time"
215+ if {([clock seconds] - $start_time ) >= $max_busy_duration } {
216+ return -code error " busy bit still set after\
217+ $max_busy_duration seconds (see busy_duration)"
209218 }
210219 set abstractcs [riscv dmi_read $ABSTRACTCS_ADDR ]
211220 }
212221
213222 set cmderr [expr {($abstractcs & 0x700) >> 8}]
214223 if {$cmderr != 0} {
215224 riscv dmi_write $ABSTRACTCS_ADDR 0x700
216- return -code error " problem with abstract command execution, \
225+ return -code error " problem with abstract command execution,\
217226 error code : $cmderr "
218227 }
219228 }
@@ -364,6 +373,7 @@ proc sc_fpga_set_busy_duration {value} {
364373}
365374
366375proc sc_fpga_riscv_csr_read {csr_num {xlen 64}} {
376+ _SC_INTERNALS::sc_lib_require_disabled_background_poll
367377 _SC_INTERNALS::sc_lib_require_halted_and_check_csr $csr_num
368378
369379 _SC_INTERNALS::sc_lib_riscv_csr_impl $csr_num 0 0 $xlen
@@ -379,6 +389,7 @@ proc sc_fpga_riscv_csr_read {csr_num {xlen 64}} {
379389}
380390
381391proc sc_fpga_riscv_csr_write {csr_num value {xlen 64}} {
392+ _SC_INTERNALS::sc_lib_require_disabled_background_poll
382393 _SC_INTERNALS::sc_lib_require_halted_and_check_csr $csr_num
383394
384395 set DATA_0 0x04
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