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jservjserv
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Merge pull request #373 from visitorckw/fix-RV32A
Fix several critical errors in RV32A
2 parents 8ea93eb + ffd0e0b commit 082e007

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+72
-34
lines changed

1 file changed

+72
-34
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‎src/rv32_template.c

Lines changed: 72 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -1315,8 +1315,10 @@ GEN({
13151315
RVOP(
13161316
lrw,
13171317
{
1318+
const uint32_t addr = rv->X[ir->rs1];
1319+
RV_EXC_MISALIGN_HANDLER(3, load, false, 1);
13181320
if (ir->rd)
1319-
rv->X[ir->rd] = rv->io.mem_read_w(rv->X[ir->rs1]);
1321+
rv->X[ir->rd] = rv->io.mem_read_w(addr);
13201322
/* skip registration of the 'reservation set'
13211323
* FIXME: uimplemented
13221324
*/
@@ -1332,7 +1334,9 @@ RVOP(
13321334
/* assume the 'reservation set' is valid
13331335
* FIXME: unimplemented
13341336
*/
1335-
rv->io.mem_write_w(rv->X[ir->rs1], rv->X[ir->rs2]);
1337+
const uint32_t addr = rv->X[ir->rs1];
1338+
RV_EXC_MISALIGN_HANDLER(3, store, false, 1);
1339+
rv->io.mem_write_w(addr, rv->X[ir->rs2]);
13361340
rv->X[ir->rd] = 0;
13371341
},
13381342
GEN({
@@ -1343,9 +1347,13 @@ RVOP(
13431347
RVOP(
13441348
amoswapw,
13451349
{
1350+
const uint32_t addr = rv->X[ir->rs1];
1351+
RV_EXC_MISALIGN_HANDLER(3, load, false, 1);
1352+
const uint32_t value1 = rv->io.mem_read_w(rv->X[ir->rs1]);
1353+
const uint32_t value2 = rv->X[ir->rs2];
13461354
if (ir->rd)
1347-
rv->X[ir->rd] = rv->io.mem_read_w(ir->rs1);
1348-
rv->io.mem_write_s(ir->rs1, rv->X[ir->rs2]);
1355+
rv->X[ir->rd] = value1;
1356+
rv->io.mem_write_w(addr, value2);
13491357
},
13501358
GEN({
13511359
assert; /* FIXME: Implement */
@@ -1355,10 +1363,14 @@ RVOP(
13551363
RVOP(
13561364
amoaddw,
13571365
{
1366+
const uint32_t addr = rv->X[ir->rs1];
1367+
RV_EXC_MISALIGN_HANDLER(3, load, false, 1);
1368+
const uint32_t value1 = rv->io.mem_read_w(rv->X[ir->rs1]);
1369+
const uint32_t value2 = rv->X[ir->rs2];
13581370
if (ir->rd)
1359-
rv->X[ir->rd] = rv->io.mem_read_w(ir->rs1);
1360-
const int32_t res = (int32_t) rv->X[ir->rd] + (int32_t) rv->X[ir->rs2];
1361-
rv->io.mem_write_s(ir->rs1, res);
1371+
rv->X[ir->rd] = value1;
1372+
const uint32_t res = value1 + value2;
1373+
rv->io.mem_write_w(addr, res);
13621374
},
13631375
GEN({
13641376
assert; /* FIXME: Implement */
@@ -1368,10 +1380,14 @@ RVOP(
13681380
RVOP(
13691381
amoxorw,
13701382
{
1383+
const uint32_t addr = rv->X[ir->rs1];
1384+
RV_EXC_MISALIGN_HANDLER(3, load, false, 1);
1385+
const uint32_t value1 = rv->io.mem_read_w(rv->X[ir->rs1]);
1386+
const uint32_t value2 = rv->X[ir->rs2];
13711387
if (ir->rd)
1372-
rv->X[ir->rd] = rv->io.mem_read_w(ir->rs1);
1373-
const int32_t res = rv->X[ir->rd] ^ rv->X[ir->rs2];
1374-
rv->io.mem_write_s(ir->rs1, res);
1388+
rv->X[ir->rd] = value1;
1389+
const uint32_t res = value1 ^ value2;
1390+
rv->io.mem_write_w(addr, res);
13751391
},
13761392
GEN({
13771393
assert; /* FIXME: Implement */
@@ -1381,10 +1397,14 @@ RVOP(
13811397
RVOP(
13821398
amoandw,
13831399
{
1400+
const uint32_t addr = rv->X[ir->rs1];
1401+
RV_EXC_MISALIGN_HANDLER(3, load, false, 1);
1402+
const uint32_t value1 = rv->io.mem_read_w(rv->X[ir->rs1]);
1403+
const uint32_t value2 = rv->X[ir->rs2];
13841404
if (ir->rd)
1385-
rv->X[ir->rd] = rv->io.mem_read_w(ir->rs1);
1386-
const int32_t res = rv->X[ir->rd] & rv->X[ir->rs2];
1387-
rv->io.mem_write_s(ir->rs1, res);
1405+
rv->X[ir->rd] = value1;
1406+
const uint32_t res = value1 & value2;
1407+
rv->io.mem_write_w(addr, res);
13881408
},
13891409
GEN({
13901410
assert; /* FIXME: Implement */
@@ -1394,10 +1414,14 @@ RVOP(
13941414
RVOP(
13951415
amoorw,
13961416
{
1417+
const uint32_t addr = rv->X[ir->rs1];
1418+
RV_EXC_MISALIGN_HANDLER(3, load, false, 1);
1419+
const uint32_t value1 = rv->io.mem_read_w(rv->X[ir->rs1]);
1420+
const uint32_t value2 = rv->X[ir->rs2];
13971421
if (ir->rd)
1398-
rv->X[ir->rd] = rv->io.mem_read_w(ir->rs1);
1399-
const int32_t res = rv->X[ir->rd] | rv->X[ir->rs2];
1400-
rv->io.mem_write_s(ir->rs1, res);
1422+
rv->X[ir->rd] = value1;
1423+
const uint32_t res = value1 | value2;
1424+
rv->io.mem_write_w(addr, res);
14011425
},
14021426
GEN({
14031427
assert; /* FIXME: Implement */
@@ -1407,12 +1431,16 @@ RVOP(
14071431
RVOP(
14081432
amominw,
14091433
{
1434+
const uint32_t addr = rv->X[ir->rs1];
1435+
RV_EXC_MISALIGN_HANDLER(3, load, false, 1);
1436+
const uint32_t value1 = rv->io.mem_read_w(rv->X[ir->rs1]);
1437+
const uint32_t value2 = rv->X[ir->rs2];
14101438
if (ir->rd)
1411-
rv->X[ir->rd] = rv->io.mem_read_w(ir->rs1);
1412-
const int32_t a = rv->X[ir->rd];
1413-
const int32_t b = rv->X[ir->rs2];
1414-
const uint32_t res = a < b ? rv->X[ir->rd] : rv->X[ir->rs2];
1415-
rv->io.mem_write_s(ir->rs1, res);
1439+
rv->X[ir->rd] = value1;
1440+
const int32_t a = value1;
1441+
const int32_t b = value2;
1442+
const uint32_t res = a < b ? value1 : value2;
1443+
rv->io.mem_write_w(addr, res);
14161444
},
14171445
GEN({
14181446
assert; /* FIXME: Implement */
@@ -1422,12 +1450,16 @@ RVOP(
14221450
RVOP(
14231451
amomaxw,
14241452
{
1453+
const uint32_t addr = rv->X[ir->rs1];
1454+
RV_EXC_MISALIGN_HANDLER(3, load, false, 1);
1455+
const uint32_t value1 = rv->io.mem_read_w(rv->X[ir->rs1]);
1456+
const uint32_t value2 = rv->X[ir->rs2];
14251457
if (ir->rd)
1426-
rv->X[ir->rd] = rv->io.mem_read_w(ir->rs1);
1427-
const int32_t a = rv->X[ir->rd];
1428-
const int32_t b = rv->X[ir->rs2];
1429-
const uint32_t res = a > b ? rv->X[ir->rd] : rv->X[ir->rs2];
1430-
rv->io.mem_write_s(ir->rs1, res);
1458+
rv->X[ir->rd] = value1;
1459+
const int32_t a = value1;
1460+
const int32_t b = value2;
1461+
const uint32_t res = a > b ? value1 : value2;
1462+
rv->io.mem_write_w(addr, res);
14311463
},
14321464
GEN({
14331465
assert; /* FIXME: Implement */
@@ -1437,11 +1469,14 @@ RVOP(
14371469
RVOP(
14381470
amominuw,
14391471
{
1472+
const uint32_t addr = rv->X[ir->rs1];
1473+
RV_EXC_MISALIGN_HANDLER(3, load, false, 1);
1474+
const uint32_t value1 = rv->io.mem_read_w(rv->X[ir->rs1]);
1475+
const uint32_t value2 = rv->X[ir->rs2];
14401476
if (ir->rd)
1441-
rv->X[ir->rd] = rv->io.mem_read_w(ir->rs1);
1442-
const uint32_t ures =
1443-
rv->X[ir->rd] < rv->X[ir->rs2] ? rv->X[ir->rd] : rv->X[ir->rs2];
1444-
rv->io.mem_write_s(ir->rs1, ures);
1477+
rv->X[ir->rd] = value1;
1478+
const uint32_t ures = value1 < value2 ? value1 : value2;
1479+
rv->io.mem_write_w(addr, ures);
14451480
},
14461481
GEN({
14471482
assert; /* FIXME: Implement */
@@ -1451,11 +1486,14 @@ RVOP(
14511486
RVOP(
14521487
amomaxuw,
14531488
{
1489+
const uint32_t addr = rv->X[ir->rs1];
1490+
RV_EXC_MISALIGN_HANDLER(3, load, false, 1);
1491+
const uint32_t value1 = rv->io.mem_read_w(rv->X[ir->rs1]);
1492+
const uint32_t value2 = rv->X[ir->rs2];
14541493
if (ir->rd)
1455-
rv->X[ir->rd] = rv->io.mem_read_w(ir->rs1);
1456-
const uint32_t ures =
1457-
rv->X[ir->rd] > rv->X[ir->rs2] ? rv->X[ir->rd] : rv->X[ir->rs2];
1458-
rv->io.mem_write_s(ir->rs1, ures);
1494+
rv->X[ir->rd] = value1;
1495+
const uint32_t ures = value1 > value2 ? value1 : value2;
1496+
rv->io.mem_write_w(addr, ures);
14591497
},
14601498
GEN({
14611499
assert; /* FIXME: Implement */

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