Add support for the RV32E base ISA variant

The RV32E variant reduces the general-purpose registers to 16, optimizing
the architecture for resource-constrained embedded microcontrollers.

This addition enhances compatibility with the RISC-V specification and
targets low-power, minimal-complexity systems.

Author: eleanorLYJ

Makefile

@@ -127,6 +127,10 @@ endif
 ENABLE_EXT_C ?= 1
 $(call set-feature, EXT_C)
 
+# RV32E Base Integer Instruction Set
+ENABLE_EXT_E ?= 0
+$(call set-feature, EXT_E)
+
 # Control and Status Register (CSR)
 ENABLE_Zicsr ?= 1
 $(call set-feature, Zicsr)

src/feature.h

@@ -27,6 +27,11 @@
 #define RV32_FEATURE_EXT_C 1
 #endif
 
+/* RV32E Base Integer Instruction Set */
+#ifndef RV32_FEATURE_EXT_E
+#define RV32_FEATURE_EXT_E 0
+#endif
+
 /* Control and Status Register (CSR) */
 #ifndef RV32_FEATURE_Zicsr
 #define RV32_FEATURE_Zicsr 1

src/riscv.c

@@ -769,10 +769,15 @@ void rv_reset(riscv_t *rv, riscv_word_t pc)
     rv->csr_mtvec = 0;
     rv->csr_cycle = 0;
     rv->csr_mstatus = 0;
-    rv->csr_misa |= MISA_SUPER | MISA_USER | MISA_I;
+    rv->csr_misa |= MISA_SUPER | MISA_USER;
     rv->csr_mvendorid = RV_MVENDORID;
     rv->csr_marchid = RV_MARCHID;
     rv->csr_mimpid = RV_MIMPID;
+#if !RV32_HAS(EXT_E)
+    rv->csr_misa |= MISA_I;
+#else
+    rv->csr_misa |= MISA_E;
+#endif
 #if RV32_HAS(EXT_A)
     rv->csr_misa |= MISA_A;
 #endif

src/riscv.h

@@ -33,6 +33,7 @@
 extern "C" {
 #endif
 
+#if !RV32_HAS(EXT_E)
 #define RV_REGS_LIST                                   \
     _(zero) /* hard-wired zero, ignoring any writes */ \
     _(ra)   /* return address */                       \
@@ -66,6 +67,25 @@ extern "C" {
     _(t4)                                              \
     _(t5)                                              \
     _(t6)
+#else
+#define RV_REGS_LIST                                   \
+    _(zero) /* hard-wired zero, ignoring any writes */ \
+    _(ra)   /* return address */                       \
+    _(sp)   /* stack pointer */                        \
+    _(gp)   /* global pointer */                       \
+    _(tp)   /* thread pointer */                       \
+    _(t0)   /* temporary/alternate link register */    \
+    _(t1)   /* temporaries */                          \
+    _(t2)                                              \
+    _(s0) /* saved register/frame pointer */           \
+    _(s1)                                              \
+    _(a0) /* function arguments / return values */     \
+    _(a1)                                              \
+    _(a2) /* function arguments */                     \
+    _(a3)                                              \
+    _(a4)                                              \
+    _(a5)
+#endif
 
 /* RISC-V registers (mnemonics, ABI names)
  *
@@ -96,6 +116,7 @@ enum {
 #define MISA_A (1 << ('A' - 'A'))
 #define MISA_F (1 << ('F' - 'A'))
 #define MISA_C (1 << ('C' - 'A'))
+#define MISA_E (1 << ('E' - 'A'))
 
 /* The mstatus register keeps track of and controls the hart’s current operating
  * state */

src/syscall.c

@@ -466,8 +466,12 @@ static void syscall_sbi_rst(riscv_t *rv)
 
 void syscall_handler(riscv_t *rv)
 {
-    /* get the syscall number */
+/* get the syscall number */
+#if !RV32_HAS(EXT_E)
     riscv_word_t syscall = rv_get_reg(rv, rv_reg_a7);
+#else
+    riscv_word_t syscall = rv_get_reg(rv, rv_reg_t0);
+#endif
 
     switch (syscall) { /* dispatch system call */
 #define _(name, number)     \